JAJSS77I September   2002  – November 2023 UCC27321 , UCC27322 , UCC37321 , UCC37322

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Related Products
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Power Dissipation Ratings
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Source and Sink Capabilities during Miller Plateau
      4. 8.3.4 Enable
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-to-Output Configuration
        2. 9.2.2.2 Input Threshold Type
        3. 9.2.2.3 VDD Bias Supply Voltage
        4. 9.2.2.4 Peak Source and Sink Currents
        5. 9.2.2.5 Enable and Disable Function
        6. 9.2.2.6 Propagation Delay
        7. 9.2.2.7 Power Dissipation
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1.     40
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • P|8
  • DGN|8
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VDD = 4.5 V to 15 V, TA = –40°C to +105°C for UCC2732x, TA = 0°C to 70°C for UCC3732x, TA = TJ, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT (IN)
VIN_H, logic 1 input threshold1.62.22.5V
VIN_L, logic 0 input threshold0.81.21.5V
Input current0 V ≤ VIN ≤ VDD–10010µA
OUTPUT (OUT)
Peak output current(1)VDD = 14 V,9A
Output resistance high(2)IOUT = –10 mA0.61.5Ω
Output resistance low(2)IOUT = 10 mA0.41Ω
OVERALL
IDD, static operating currentUCC37321
UCC27321		IN = LOW, EN = LOW, VDD = 15 V150225µA
IN = HIGH, EN = LOW, VDD = 15 V440650
IN = LOW, EN = HIGH, VDD = 15 V370550
IN = HIGH, EN = HIGH, VDD = 15 V370550
UCC37322
UCC27322		IN = LOW, EN = LOW, VDD = 15 V150225
IN = HIGH, EN = LOW, VDD = 15 V450650
IN = LOW, EN = HIGH, VDD = 15 V75125
IN = HIGH, EN = HIGH, VDD = 15 V6751000
ENABLE (ENBL)
VEN_H, high-level enable voltageLOW to HIGH transition1.72.22.7V
VEN_L, low-level enable voltageHIGH to LOW transition1.11.62V
Hysteresis0.250.550.90
RENBL, enable impedanceVDD = 14 V, ENBL = GND75100135kΩ
(1) Not tested in production.
(2) Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure.