JAJSOH3 October   2023 UCC27332-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Power On Reset
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
    4. 7.4 Device Functional Modes
  9. 8  Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Driving MOSFET
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input-to-Output Configuration
          2. 8.2.1.2.2 Input Threshold Type
          3. 8.2.1.2.3 VDD Bias Supply Voltage
          4. 8.2.1.2.4 Peak Source and Sink Currents
          5. 8.2.1.2.5 Enable and Disable Function
          6. 8.2.1.2.6 Propagation Delay and Minimum Input Pulse Width
          7. 8.2.1.2.7 Power Dissipation
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Consideration
  10. 9 Device and Documentation Support
    1. 9.1 サード・パーティ製品に関する免責事項
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

The UCC27332-Q1 deviceis a single-channel, high-speed, gate drivers capable of effectively driving MOSFET, and GaN power switches with 9-A source and 9-A sink (symmetrical drive) peak current. A strong source and sink capability boost immunity against a parasitic Miller turnon effect. The UCC27332-Q1 device can be directly connected to the gate driver transformer or line driver transformer as the inputs of UCC27332-Q1 can handle –5V. The driver has a good transient handling capability on its output due to reverse currents, as well as rail-to-rail drive capability and small propagation delay, typically 23 ns.

The input threshold of UCC27332-Q1 is compatible to TTL low-voltage logic, which is fixed and independent of VDD supply voltage. The driver can also work with CMOS based controllers as long as the threshold requirement is met. The 1-V typical hysteresis offers excellent noise immunity.

The driver has an EN pin with fixed TTL compatible threshold. EN is internally pulled up; pulling EN low disables the driver, while leaving EN open provides normal operation. The EN pin can be used as an additional input with similar performance as the IN pin.

Table 7-1 UCC27332-Q1 Features and Benefits
FEATURE BENEFIT
–5 V IN and EN capability Enhanced signal reliability and device robustness in noisy environments that experience ground bounce on the gate driver.
High source and sink current capability 9 A High current capability helps drive large gate charge loads to minimize switching losses.
Low 25 ns (typ) propagation delay. Extremely low pulse transmission distortion
Wide VDD operating range of 4.5 V to 18 V Flexibility in system design

EN can float

Safe operation when the output of the controller ties to the EN pin in tristate
Strong sink current (9 A) and low pulldown impedance (0.4Ω) High immunity to high dV/dt Miller turnon events
TTL compatible input threshold logic with wide hysteresis Enhanced noise immunity, while retaining compatibility with microcontroller logic level input signals (3.3 V, 5 V) optimized for digital power