SLUS704C FEBRUARY   2007  – December 2014 UCC27423-EP , UCC27424-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Power Dissipation Ratings
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stage
      2. 7.3.2 Output Stage
      3. 7.3.3 Operational Waveforms and Circuit Layout
      4. 7.3.4 VDD
      5. 7.3.5 Enable
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source/Sink Capabilities During Miller Plateau
        2. 8.2.2.2 Parallel Outputs
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Drive Current and Power Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

D or DGN Package
(Top View)
po1_lus704.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ENBA 1 I Enable for driver A with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is pulled up internally to VDD with a 100-kΩ resistor for active-high operation. When the device is disabled, the output state is low, regardless of the input state.
ENBB 8 I Enable for driver B with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is pulled up internally to VDD with a 100-kΩ resistor for active-high operation. The output state when the device is disabled is low, regardless of the input state.
GND 3 — Common ground. This ground should be connected very closely to the source of the power MOSFET that the driver is driving.
INA 2 I Input A. Input signal of the A driver, which has logic-compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. Do not leave floating.
INB 4 I Input B. Input signal of the A driver, which has logic-compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. Do not leave floating.
OUTA 7 O Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
OUTB 5 O Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
VDD 6 I Supply. Supply voltage and the power input connection for this device.