SLUSAW9F February   2012  – November 2014 UCC27511 , UCC27512

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 UCC2751x Product Family
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD and Undervoltage Lockout
      2. 9.3.2 Operating Supply Current
      3. 9.3.3 Input Stage
      4. 9.3.4 Enable Function
      5. 9.3.5 Output Stage
      6. 9.3.6 Low Propagation Delays
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input-to-Output Logic
        2. 10.2.2.2 Input Threshold Type
        3. 10.2.2.3 VDD Bias Supply Voltage
        4. 10.2.2.4 Peak Source and Sink Currents
        5. 10.2.2.5 Enable and Disable Function
        6. 10.2.2.6 Propagation Delay
        7. 10.2.2.7 Thermal Information
        8. 10.2.2.8 Power Dissipation
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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8 Specifications

8.1 Absolute Maximum Ratings(1)(2)(3)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage range VDD –0.3 20 V
OUTH voltage, (UCC27511) –0.3 VDD + 0.3
OUTL voltage, (UCC27511) DC –0.3 20
Repetitive pulse less than 200 ns(5) –2 20
OUT voltage, (UCC27512) DC –0.3 VDD + 0.3
Repetitive pulse less than 200 ns(5) –2 VDD + 0.3
Output continuous current
(OUTH source current and OUTL sink current)		 IOUT_DC (source) 0.3 A
IOUT_DC (sink) 0.6
Output pulsed current (0.5 µs)
(OUTH source current and OUTL sink current)		 IOUT_pulsed(source) 4
IOUT_pulsed(sink) 8
IN+, IN–(4) –0.3 20 V
Lead temperature Soldering, 10 sec. 300 °C
Reflow 260
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into and negative out of the specified terminal. See Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
(4) Maximum voltage on input pins is not restricted by the voltage on the VDD pin.
(5) Values are verified by characterization on bench.

8.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –4000 4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –1000 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage range, VDD 4.5 12 18 V
Operating junction temperature range –40 140 °C
Input voltage, IN+ and IN- 0 18 V

8.4 Thermal Information

THERMAL METRIC UCC27511 UCC27512 UNIT
DBV WSON(1)
6 PINS 6 PINS
θJA Junction-to-ambient thermal resistance(2) 217.8 85.6 °C/W
θJCtop Junction-to-case (top) thermal resistance(3) 97.6 100.1
θJB Junction-to-board thermal resistance(4) 72.2 58.6
ψJT Junction-to-top characterization parameter(5) 8.6 7.5
ψJB Junction-to-board characterization parameter(6) 71.6 58.7
θJCbot Junction-to-case (bottom) thermal resistance(7) n/a 23.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

NOTE

Under identical power dissipation conditions, the DRS package will allow to maintain a lower die temperature than the DBV. θJA metric should be used for comparison of power dissipation capability between different packages (Refer to the Power Dissipation Section).

8.5 Electrical Characteristics

VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
BIAS CURRENTS
IDD(off) Startup current VDD = 3.4 V IN+ = VDD, IN– = GND 40 100 160 µA
IN+ = IN– = GND or IN+ = IN– = VDD 25 75 145
IN+ = GND, IN– = VDD 20 60 115
UNDERVOLTAGE LOCKOUT (UVLO)
VON Supply start threshold TA = 25°C 3.91 4.20 4.5 V
TA = –40°C to 140°C 3.70 4.20 4.65
VOFF Minimum operating voltage after supply start 3.45 3.9 4.35
VDD_H Supply voltage hysteresis 0.2 0.3 0.5
INPUTS (IN+, IN-)
VIN_H Input signal high threshold Output high for IN+ pin,
Output low for IN– pin		 2.2 2.4 V
VIN_L Input signal low threshold Output low for IN+ pin,
Output high for IN– pin		 1.0 1.2
VIN_HYS Input signal hysteresis 1.0
SOURCE/SINK CURRENT
ISRC/SNK Source/sink peak current(1) CLOAD = 0.22 µF, FSW = 1 kHz -4/+8 A
OUTPUTS (OUTH, OUTL, OUT)
VDD-VOH High output voltage VDD = 12 V
IOUTH = -10 mA		 50 90 mV
VDD = 4.5 V
IOUTH = -10 mA		 60 130
VOL Low output voltage VDD = 12
IOUTL = 10 mA		 5 6.5
VDD = 4.5 V
IOUTL = 10 mA		 5.5 10
ROH Output pull-up resistance(3) VDD = 12 V
IOUTH = -10 mA		 5.0 7.5 Ω
VDD = 4.5 V
IOUTH = -10 mA		 5.0 11.0
ROL Output pull-down resistance VDD = 12 V
IOUTL = 10 mA		 0.375 0.650
VDD = 4.5 V
IOUTL = 10 mA		 0.45 0.750
(1) Ensured by Design.
(2) See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4.
(3) ROH represents on-resistance of P-Channel MOSFET in pullup structure of the output stage of the UCC27511 and UCC27512.

Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR Rise time(2) VDD = 12 V
CLOAD = 1.8 nF, connected to OUTH and OUTL pins tied together		 8 12 ns
VDD = 4.5 V
CLOAD = 1.8 nF		 16 22
tF Fall time(2) VDD = 12 V
CLOAD = 1.8 nF, connected to OUTH and OUTL pins tied together		 7 11
VDD=4.5V
CLOAD = 1.8 nF		 7 11
tD1 IN+ to output propagation delay(2) VDD = 12 V
5-V input pulse CLOAD = 1.8 nF, connected to OUTH and OUTL pins tied together		 4 13 23
VDD = 4.5 V
5-V input pulse CLOAD = 1.8 nF, connected to OUTH and OUTL pins tied together		 4 15 26
tD2 IN- to output propagation delay(2) VDD = 12 V
CLOAD = 1.8 nF, connected to OUTH and OUTL pins tied together		 4 13 23
VDD = 4.5 V
CLOAD = 1.8 nF, connected to OUTH and OUTL pins tied together		 4 19 30
time1_lusaw9.gif
(PWM Input to IN+ Pin (IN– Pin Tied to GND), Output Represents OUTH And OUTL Pins Tied Together in the UCC27511)
Figure 1. Noninverting Configuration
time2_lusaw9.gif
(PWM Input to IN– Pin (IN+ Pin Tied to VDD), Output Represents OUTH and OUTL Pins Tied Together in the UCC27511)
Figure 2. Inverting Configuration
time3_lusaw9.gif
(Enable and Disable Signal Applied to IN+ Pin, PWM Input to IN– Pin, Output Represents OUTH and OUTL Pins Tied Together in the UCC27511)
Figure 3. Enable and Disable Function Using IN+ Pin
time4_lusaw9.gif
(Enable and Disable Signal Applied to IN– Pin, PWM Input To IN+ Pin, Output Represents OUTH and OUTL Pins Tied Together in the UCC27511)
Figure 4. Enable and Disable Function Using IN– Pin

8.6 Typical Characteristics

G001_Startup Current_lusaw9.pngFigure 5. Start-Up Current vs Temperature
G002_Operating Supply Current_lusaw9.pngFigure 7. Supply Current vs Temperature (Output In DC On/Off Condition)
G014_Input_Threshold_lusaw9.pngFigure 9. Input Threshold vs Temperature
G005_Pull-Down Resistance_lusaw9.pngFigure 11. Output Pulldown Resistance vs Temperature
G016_Fall Time_temp_lusaw9.pngFigure 13. Fall Time vs Temperature
G010_IDD_frequency_lusaw9.pngFigure 15. Operating Supply Current vs Frequency
G008_Rise Time_lusaw9.pngFigure 17. Rise Time vs Supply Voltage
G013_Idd_500kHz_lusaw9.pngFigure 6. Operating Supply Current vs Temperature (Output Switching)
G003_UVLO_lusaw9.pngFigure 8. UVLO Threshold Voltage vs Temperature
G004_Pull-Up Resistance_lusaw9.pngFigure 10. Output Pullup Resistance vs Temperature
G015_Rise Time_temp_lusaw9.pngFigure 12. Rise Time vs Temperature
G006_Propagation Delay_lusaw9.pngFigure 14. Input to Output Propagation Delay vs Temperature
G007_Propagation Delay_VDD_lusaw9.pngFigure 16. Propagation Delays vs Supply Voltage
G009_Fall Time_lusaw9.pngFigure 18. Fall Time vs Supply Voltage