JAJSEZ0B August   2014  – January 2024 UCC27511A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VDD and Undervoltage Lockout
      2. 6.3.2 Operating Supply Current
      3. 6.3.3 Input Stage
      4. 6.3.4 Enable Function
      5. 6.3.5 Output Stage
      6. 6.3.6 Low Propagation Delays
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input-to-Output Logic
        2. 7.2.2.2 Input Threshold Type
        3. 7.2.2.3 VDD Bias Supply Voltage
        4. 7.2.2.4 Peak Source and Sink Currents
        5. 7.2.2.5 Enable and Disable Function
        6. 7.2.2.6 Propagation Delay
        7. 7.2.2.7 Thermal Information
        8. 7.2.2.8 Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
BIAS CURRENTS
I(START)Startup currentVDD = 3.4 VIN+ = VDD, IN– = GND40100160µA
IN+ = IN– = GND or IN+ = IN– = VDD2575145
IN+ = GND, IN– = VDD2060115
UNDERVOLTAGE LOCKOUT (UVLO)
V(ON)Supply start thresholdTA = 25°C3.914.24.5V
TA = –40°C to 140°C3.74.24.65
V(OFF)Minimum operating voltage after supply start3.453.94.35
VDD(hys)Supply voltage hysteresis0.20.30.5
INPUTS (IN+, IN–)
VIH(IN)Input signal high thresholdOutput high for IN+ pin,
Output low for IN– pin		2.22.4V
VIL(IN)Input signal low thresholdOutput low for IN+ pin,
Output high for IN– pin		1.01.2
Vhys(IN)Input signal hysteresis1
SOURCE AND SINK CURRENT
IP(SRC)Source peak current(1)C(LOAD) = 0.22 µF, ƒS = 1 kHz–4A
IP(SNK)Sink peak current(1)C(LOAD) = 0.22 µF, ƒS = 1 kHz8A
OUTPUTS (OUTH, OUTL, OUT)
VOHHigh output voltageVDD = 12 V
I(OUTH) = –10 mA		5090mV
VDD = 4.5 V
I(OUTH) = –10 mA		60130
VOLLow output voltageVDD = 12
I(OUTL) = 10 mA		56.5
VDD = 4.5 V
I(OUTL) = 10 mA		5.510
RO(H)Output pullup resistance(2)VDD = 12 V
I(OUTH) = –10 mA		57.5Ω
VDD = 4.5 V
I(OUTH) = –10 mA		511
RO(L)Output pulldown resistanceVDD = 12 V
I(OUTL) = 10 mA		0.3750.65
VDD = 4.5 V
I(OUTL) = 10 mA		0.450.75
(1) Ensured by Design.
(2) RO(H) represents the on-resistance of P-channel MOSFET in pullup structure of the output stage of the UCC27511A-Q1 device.