The UCC27511A-Q1 device has and internal undervoltage-lockout (UVLO) protection feature on the V_DD pin supply circuit blocks. Whenever the driver is in UVLO condition (for example when the V_DD voltage is less than V_(ON) during power up and when the V_DD voltage is less than V_(OFF) during power down), this circuit holds all outputs low, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis prevents chatter when low V_DD supply voltages have noise from the power supply and also when there are droops in the V_DD bias voltage when the system commences switching and a sudden increase in I_DD occurs. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging GaN wide band-gap power-semiconductor devices.

For example, at power up, the UCC27511A-Q1 driver output remains LOW until the V_DD voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with V_DD until steady-state V_DD is reached. In the non-inverting operation (PWM signal applied to IN+ pin) shown in Figure 6-1, the output remains LOW until the UVLO threshold is reached, and then the output is IN–phase with the input. In the inverting operation (PWM signal applied to IN– pin) shown in Figure 6-2 the output remains low until the UVLO threshold is reached, and then the output is out-phase with the input. In both cases, the unused input pin must be properly biased to enable the output. Note that in these devices the output turns to high state only if the IN+ pin is high and the IN– pin is low after the UVLO threshold is reached.

Because the driver draws current from the V_DD pin to bias all internal circuits, for the best high-speed circuit performance, two V_DD-bypass capacitors are recommended to prevent noise problems. The use of surface-mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to the V_DD to GND pins of the gate driver. In addition, to help deliver the high-current peaks required by the load, a larger capacitor (such as one with a value of 1 μF) with relatively low ESR should be connected in parallel and close proximity. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels and switching frequencies in the application.

Figure 6-1 Power-Up (Non-Inverting Drive)

Figure 6-2 Power-Up (Inverting Drive)