SLUSAQ3H November   2011  – June 2024 UCC27523 , UCC27525 , UCC27526

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Undervoltage Lockout
      2. 7.3.2 Operating Supply Current
      3. 7.3.3 Input Stage
      4. 7.3.4 Enable Function
      5. 7.3.5 Output Stage
      6. 7.3.6 Low Propagation Delays and Tightly Matched Outputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input-to-Output Logic
        2. 8.2.2.2 Enable and Disable Function
        3. 8.2.2.3 VDD Bias Supply Voltage
        4. 8.2.2.4 Propagation Delay
        5. 8.2.2.5 Drive Current and Power Dissipation
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Operating Supply Current

The UCC2752x products feature very low quiescent IDD currents. The typical operating-supply current in UVLO state and fully on state (under static and switching conditions) are summarized in Figure 6-5, Figure 6-6 and Figure 6-7. The IDD current when the device is fully on and outputs are in a static state (DC high or DC low, refer Figure 6-6) represents lowest quiescent IDD current when all the internal logic circuits of the device are fully operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current due to switching and finally any current related to pullup resistors on the enable pins and inverting input pins. For example when the inverting Input pins are pulled low additional current is drawn from VDD supply through the pullup resistors (refer to Figure 7-1 though Figure 7-3). Knowing the operating frequency (fSW) and the MOSFET gate (QG) charge at the drive voltage being used, the average IOUT current can be calculated as product of QG and fSW.

A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages under 1.8-nF switching load in both channels is provided in Figure 6-17. The strikingly linear variation and close correlation with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device attesting to its high-speed characteristics.