SLUSBP4C August   2013  – June 2024 UCC27524A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Supply Current
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
    4. 6.4 Low Propagation Delays and Tightly Matched Outputs
    5. 6.5 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD and Undervoltage Lockout
        2. 7.2.2.2 Drive Current and Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

Unless otherwise noted, VDD = 12 V, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, no load on the output. Typical condition specifications are at 25°C.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
BIAS CURRENTS (DGN)
IVDDqVDD quiescent supply currentVINx = 3.3 V, VDD = 3.4 V, ENx = VDD300450μA
IVDDVDD static supply currentVINx = 3.3 V, ENx = VDD0.61.0mA
IVDDVDD static supply currentVINx = 0 V, ENx = VDD0.71.0mA
IVDDOVDD operating currentfSW = 1000 kHz, ENx = VDD, VINx = 0 V – 3.3 V PWM3.23.8mA
IDISVDD disable currentVINx = 3.3 V, ENx = 0 V0.81.1mA
BIAS CURRENTS (D)
IDD(off) Start-up current VDD = 3.4 V,
INA = VDD,
INB = VDD		 55 110 175 μA
VDD = 3.4 V,
INA = GND,
INB = GND		 25 75 145
UNDERVOLTAGE LOCKOUT (UVLO) (DGN)
VVDD_ONVDD UVLO rising threshold3.84.14.4V
VVDD_OFFVDD UVLO falling threshold3.53.84.1V
VVDD_HYSVDD UVLO hysteresis0.3V
UNDERVOLTAGE LOCKOUT (UVLO) (D)
VON Supply start threshold TJ = 25°C 3.91 4.2 4.5 V
TJ = –40°C to 140°C 3.7 4.2 4.65
VOFF Minimum operating voltage after supply start 3.4 3.9 4.4
VDD_H Supply voltage hysteresis 0.2 0.3 0.5
INPUT (INA, INB) (DGN)
VINx_HInput signal high thresholdOutput High, ENx = HIGH1.822.3V
VINx_LInput signal low thresholdOutput Low, ENx = HIGH0.811.2V
VINx_HYSInput signal hysteresis1V
RINxINx pin pulldown resistorINx = 3.3 V120kΩ
INPUT (INA, INB) (D)
VIN_H Input signal high threshold Output high for non-inverting input pins
Output low for inverting input pins		 1.9 2.1 2.3 V
VIN_L Input signal low threshold Output low for non-inverting input pins
Output high for inverting input pins		 1 1.2 1.4
VIN_HYS Input hysteresis 0.7 0.9 1.1
ENABLE (ENA, ENB) (DGN)
VENx_HEnable signal high thresholdOutput High, INx = HIGH1.822.3V
VENx_LEnable signal low thresholdOutput Low, INx = HIGH0.811.2V
VENx_HYSEnable signal hysteresis1V
RENxEN pin pullup resistanceENx = 0 V200kΩ
ENABLE (ENA, ENB) (D)
VEN_H Enable signal high threshold Output enabled 1.9 2.1 2.3 V
VEN_L Enable signal low threshold Output disabled 0.95 1.15 1.35
VEN_HYS Enable hysteresis 0.7 0.95 1.1
OUTPUTS (OUTA, OUTB) (DGN)
ISRC(1)Peak output source currentVDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz5A
ISNK(1)Peak output sink currentVDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz–5A
ROH(2)Pullup resistanceIOUT = –50 mA, See Section 6.3.4.58.5Ω
ROLPulldown resistanceIOUT = 50 mA0.61.1Ω
OUTPUTS (OUTA, OUTB) (D)
ISNK/SRC(1) Sink/source peak current CLOAD = 0.22 µF, FSW = 1 kHz ±5 A
VDD-VOH High output voltage IOUT = –10 mA 0.075 V
VOL Low output voltage IOUT = 10 mA 0.01
ROH(2) Output pullup resistance IOUT = –10 mA 2.5 5 7.5 Ω
ROL Output pulldown resistance IOUT = 10 mA 0.15 0.5 1 Ω
(1) Parameter not tested in production.
(2) Output pullup resistance in this table is a DC measurement that measures resistance of PMOS structure only (not N-channel structure).