SLUSBP4C August   2013  – June 2024 UCC27524A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Supply Current
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
    4. 6.4 Low Propagation Delays and Tightly Matched Outputs
    5. 6.5 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD and Undervoltage Lockout
        2. 7.2.2.2 Drive Current and Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Switching Characteristics

Unless otherwise noted, VDD = VEN = 12 V, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, no load on the output. Typical condition specifications are at 25°C (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DGN package
tRx Rise time(2) CLOAD = 1.8 nF, 20% to 80%, Vin = 0 V – 3.3 V 6 10 ns
tFx Fall time(2) CLOAD = 1.8 nF, 90% to 10%, Vin = 0 V – 3.3 V 10 14 ns
tD1x Turn-on propagation delay CLOAD = 1.8 nF, VINx_H of the input rise to 10% of output rise, Vin = 0 V – 3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C 17 27 ns
tD2x Turn-off propagation delay CLOAD = 1.8 nF, VINx_L of the input fall to 90% of output fall, Vin = 0 V – 3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C 17 27 ns
tD3x Enable propagation delay CLOAD = 1.8 nF, VENx_H of the enable rise to 10% of output rise, Vin = 0 V – 3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C 17 27 ns
tD4x Disable propagation delay CLOAD = 1.8 nF, VENx_L of the enable fall to 90% of output fall, Vin = 0 V – 3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C 17 27 ns
tM Delay matching between two channels CLOAD = 1.8 nF, Vin = 0 V – 3.3 V, Fsw = 500 kHz, 50% duty cycle, INA = INB, |tRA – tRB|, |tFA – tFB| 1 2 ns
tPWmin Minimum input pulse width CL = 1.8 nF, Vin = 0 V – 3.3 V, Fsw = 500 kHz, Vo > 1.5 V 10 15 ns
D package
tR Rise time CLOAD = 1.8 nF 7 18 ns
tF Fall time CLOAD = 1.8 nF 6 10 ns
tM Delay matching between 2 channels INA = INB, OUTA and OUTB at 50% transition point 1 4 ns
tPW Minimum input pulse width that changes the output state 15 25 ns
tD1, tD2 Input to output propagation delay CLOAD = 1.8 nF, 5-V input pulse 6 13 23 ns
tD3, tD4 EN to output propagation delay CLOAD = 1.8 nF, 5-V enable pulse 6 13 23 ns
(1) Switching parameters are not tested in production.
(2) See the timing diagrams in Figure 5-1 and Figure 5-2.