JAJSC56F December   2012  – March 2018 UCC27611

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Undervoltage Lockout
      2. 7.3.2 Operating Supply Current
      3. 7.3.3 Input Stage
      4. 7.3.4 Enable Function
      5. 7.3.5 Output Stage
      6. 7.3.6 Low Propagation Delays
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Supply Voltage
        2. 8.2.2.2 Input Configuration
        3. 8.2.2.3 Output Configuration
        4. 8.2.2.4 Power Dissipation
        5. 8.2.2.5 Thermal Considerations
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VDD = 12 V, TA = TJ = –40 °C to 140 °C, 2-µF capacitor from VDD to GND and from VREF to GND. Currents are positive into, negative out of the specified terminal. OUTH and OUTL are tied together. (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS CURRENT
IDD(off) Start-up current VDD = 3, IN+ = VDD,
IN– = GND		 100 180 μA
IN+ = GND, IN– = VDD 75 160
UNDER VOLTAGE LOCKOUT (UVLO)
VDD(on) Supply start threshold 3.55 3.8 4.15 V
VDD(off) Minimum operating voltage after supply start 3.3 3.55 3.9 V
VDD_H Supply voltage hysteresis 0.25 V
INPUTS (IN+, IN–)
VIN_L Input signal low threshold Output high for IN– pin,
Output Low for IN+ pin		 0.9 1.1 1.3 V
VIN_H Input signal high threshold Output high for IN+ pin,
Output low for IN– pin		 1.85 2.05 2.25 V
VIN_HYS Input signal hysteresis 0.7 0.95 1.2 V
VREF
VREF VREF regulator output 4.75 5 5.15 V
VREF_line VREF line regulation VDD from 6 V to 18 V 0.05 V
VREF_load VREF load regulation IR from 0 mA to 50 mA 0.075 V
ISCC Short circuit current –90 –75 –60 mA
OUTPUTS (OUTH/OUTL AND OUT)
ISRC/SNK Source peak current (OUTH) / sink peak current (OUTL)(2) CLOAD = 0.22 µF, FSW = 1 kHz, (2) –4/+6 A
VOH OUTH high voltage IOUTH = –10 mA VDD –0.05 V
VOL OUTL low voltage IOUTL = 10 mA 0.02 V
ROH OUTH pullup resistance TA = 25 °C,
IOUT = –25 mA to –50 mA		 1 Ω
TA = –40 °C to 140 °C,
IOUT = –50 mA		 2
ROL OUTH pulldown resistance TA = 25 °C,
IOUT = 25 mA to 50 mA		 0.35 Ω
TA = –40°C to 140°C,
IOUT = 50 mA		 1.5
(1) Device operational with output switching.
(2) Ensured by design, not tested in production.