JAJSDL2A
August 2017 – August 2018
UCC27712-Q1
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
概略回路図
標準的な伝播遅延の比較
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Dynamic Electrical Characteristics
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VDD and Under Voltage Lockout
8.3.2
Input and Output Logic Table
8.3.3
Input Stage
8.3.4
Output Stage
8.3.5
Level Shift
8.3.6
Low Propagation Delays and Tightly Matched Outputs
8.3.7
Parasitic Diode Structure
8.4
Device Functional Modes
8.4.1
Minimum Input Pulse Operation
8.4.2
Output Interlock and Dead Time
8.4.3
Operation Under 100% Duty Cycle Condition
8.4.4
Operation Under Negative HS Voltage Condition
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
9.2.2.2
Selecting Bootstrap Capacitor (CBOOT)
9.2.2.3
Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
9.2.2.4
Selecting Bootstrap Resistor (RBOOT)
9.2.2.5
Selecting Gate Resistor RON/ROFF
9.2.2.6
Selecting Bootstrap Diode
9.2.2.7
Estimate the UCC27712-Q1 Power Losses (PUCC27712-Q1)
9.2.2.8
Estimating Junction Temperature
9.2.2.9
Operation With IGBT's
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントのサポート
12.1.1
関連資料
12.2
関連リンク
12.3
コミュニティ・リソース
12.4
商標
12.5
静電気放電に関する注意事項
12.6
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|8
MSOI002K
サーマルパッド・メカニカル・データ
発注情報
jajsdl2a_oa
11.2
Layout Example
Figure 53.
UCC27712
-Q1
Layout Example