JAJSFJ9B December   2017  – October 2019 UCC28064A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Principles of Operation
      2. 8.3.2  Natural Interleaving
      3. 8.3.3  On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward compensation
      4. 8.3.4  Distortion Reduction
      5. 8.3.5  Zero-Current Detection and Valley Switching
      6. 8.3.6  Phase Management and Light-Load Operation
      7. 8.3.7  Burst Mode Operation
      8. 8.3.8  External Disable
      9. 8.3.9  Improved Error Amplifier
      10. 8.3.10 Soft Start
      11. 8.3.11 Brownout Protection
      12. 8.3.12 Line Dropout Detection
      13. 8.3.13 VREF
      14. 8.3.14 VCC
      15. 8.3.15 System Level Protections
        1. 8.3.15.1 Failsafe OVP - Output Over-voltage Protection
        2. 8.3.15.2 Overcurrent Protection
        3. 8.3.15.3 Open-Loop Protection
        4. 8.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection
        5. 8.3.15.5 Phase-Fail Protection
        6. 8.3.15.6 CS - Open, TSET - Open and Short Protection
        7. 8.3.15.7 Thermal Shutdown Protection
        8. 8.3.15.8 Fault Logic Diagram
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Inductor Selection
        3. 9.2.2.3  ZCD Resistor Selection RZA, RZB
        4. 9.2.2.4  HVSEN
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Selecting RS For Peak Current Limiting
        7. 9.2.2.7  Power Semiconductor Selection (Q1, Q2, D1, D2)
        8. 9.2.2.8  Brownout Protection
        9. 9.2.2.9  Converter Timing
        10. 9.2.2.10 Programming VOUT
        11. 9.2.2.11 Voltage Loop Compensation
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Input Ripple Current Cancellation with Natural Interleaving
        2. 9.2.3.2 Brownout Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Package Option Addendum
    1. 12.1 Packaging Information
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
        1. 13.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, RTSET = 133 kΩ, all voltages are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC BIAS SUPPLY
VCCSHUNT VCC shunt voltage(1) IVCC = 10 mA 22 24 26 V
IVCC(UVLO) VCC current, UVLO VCC = 9.3 V prior to turn on 125 200 µA
IVCC(stby) VCC current, disabled VSENSE = 0 V 150 210 µA
IVCC(on) VCC current, enabled VSENSE = 2 V 5 8 mA
IVCC(BURST) VCC current burst mode no switching VCOMP < VBURST 650 850 µA
UNDERVOLTAGE LOCKOUT (UVLO)
VCCON VCC turnon threshold VCC rising 9.45 10.35 11.1 V
VCCOFF VCC turnoff threshold VCC falling 8.8 9.6 10.7 V
ΔVCCUVLO UVLO Hysteresis VCCON - VCCOFF 0.68 0.8 0.9 V
REFERENCE
VREF VREF output voltage, no load IVREF = 0 mA 5.82 6.00 6.18 V
ΔVREF_LOAD VREF change with load 0 mA ≤ IVREF ≤ −2 mA -6 -1 mV
ΔVREF_VCC VREF change with VCC 12 V ≤ VCC ≤ 20 V 2 10 mV
ERROR AMPLIFIER
VSENSEreg25 VSENSE input regulation voltage TA = 25°C 5.85 6 6.15 V
VSENSEreg VSENSE input regulation voltage 5.82 6 6.18 V
IVSENSE VSENSE input bias current In regulation 50 100 150 nA
VENAB VSENSE enable threshold, rising 1.15 1.25 1.35 V
VSENSE enable hysteresis 0.02 0.07 0.15 V
VCOMP_CLMP COMP high voltage, clamped VSENSE = VSENSEreg – 0.3 V 4.70 4.95 5.10 V
VCOMP_SAT COMP low voltage, saturated VSENSE = VSENSEreg + 0.3 V 0.03 0.125 V
gM1 VSENSE to COMP transconductance, small signal 0.99(VSENSEreg) < VSENSE < 1.01(VSENSEreg), COMP = 3 V 40 55 70 µS
VSENSE_gM2_SINK VSENSE high-going threshold to enable COMP large signal gain, percent Relative to VSENSEreg, COMP = 3 V 3.25 5 6.75 %
VSENSE_gM2_SOURCE VSENSE low-going threshold to enable COMP large signal gain, percent Relative to VSENSEreg, COMP = 3 V –6.75 −5 −3.25 %
gM2_SOURCE VSENSE to COMP transconductance, large signal VSENSE = VSENSEreg – 0.4 V , COMP = 3 V 210 290 370 µS
gM2_SINK VSENSE to COMP transconductance, large signal VSENSE = VSENSEreg + 0.4 V, COMP = 3 V 210 290 370 µS
ICOMP_SOURCE_MAX COMP maximum source current VSENSE = 5 V, COMP = 3 V -170 -125 -80 µA
RCOMPDCHG COMP discharge resistance HVSEN = 5.2 V, COMP = 3 V 1.6 2 2.4 kΩ
IDODCHG COMP discharge current during Dropout VSENSE = 5 V, VINAC = 0.3 V, COMP = 1V 3.2 4 4.8 µA
VLOW_OV VSENSE overvoltage threshold, rising Relative to VSENSEreg 6.5 8 9.5 %
ΔVLOW_OV_HYST VSENSE overvoltage hysteresis Relative to VLOW_OV -3 -2 -1.5 %
VHIGH_OV VSENSE 2nd overvoltage threshold, rising Relative to VSENSEreg 9.3 11 12.7 %
SOFT START
VSSTHR COMP Soft-Start threshold, falling VSENSE = 1.5 V 10 23 35 mV
ISS,FAST COMP Soft-Start current, fast SS-state, VENAB < VSENSE < VREF/2 -170 -125 -80 µA
ISS,SLOW COMP Soft-Start current, slow SS-state, VREF/2 < VSENSE < 0.88VREF -20 -16 -11.5 µA
KEOSS VSENSE End-of-Soft-Start threshold factor Percent of VSENSEreg 96.5% 98.3% 99.8%
OUTPUT MONITORING
VHV_OV_FLT HVSEN threshold to overvoltage fault HVSEN rising 4.64 4.87 5.1 V
VHV_OV_CLR HVSEN threshold to overvoltage clear HVSEN falling 4.45 4.67 4.8 V
GATE DRIVE
VGDx_H GDA, GDB output voltage, high IGDA, IGDB = −100 mA 10.7 12.4 15 V
RGDx_H GDA, GDB on-resistance, high IGDA, IGDB = −100 mA 8.8 16.7 Ω
VGDx_L GDA, GDB output voltage, low IGDA, IGDB = 100 mA 0.18 0.32 V
RGDx_L GDA, GDB on-resistance, low IGDA, IGDB = 100 mA 2 3.2 Ω
VGDx_H_VCCH GDA, GDB output voltage high, clamped VCC = 20 V, IGDA, IGDB = −5 mA 11.8 13.5 15 V
VGDx_H_VCCL GDA, GDB output voltage high, low VCC VCC = 12 V, IGDA, IGDB = −5 mA 10 10.5 11.5 V
VGDx_L_UVLO GDA, GDB output voltage, UVLO VCC = 3.0 V, IGDA, IGDB = 2.5 mA 100 200 mV
tGDx_RISE Rise time 1 V to 9 V, CLOAD = 1 nF 18 30 ns
tGDx_FALL Fall time 9 V to 1 V, CLOAD = 1 nF 12 25 ns
ZERO CURRENT DETECTOR
VZCDx_TRIG ZCDA, ZCDB voltage threshold, falling 0.8 1 1.2 V
VZCDx_ARM ZCDA, ZCDB voltage threshold, rising 1.5 1.7 1.9 V
VZCDx_CLMP_H ZCDA, ZCDB clamp, high IZCDA = +2 mA, IZCDB = +2 mA 2.6 3 3.4 V
VZCDx_CLMP_L ZCDA, ZCDB clamp, low IZCDA = −2 mA, IZCDB = −2 mA -0.40 −0.2 0 V
IZCDx ZCDA, ZCDB input bias current ZCDA = 1.4 V, ZCDB = 1.4 V -0.5 0 0.5 µA
tZCDx_DEL ZCDA, ZCDB delay to GDA, GDB outputs From ZCDx input falling to 1 V to respective gate drive output rising 10% 50 100 ns
tZCDx_BLNK ZCDA, ZCDB blanking time From GDx rising to GDx falling 100 ns
CURRENT SENSE
ICS CS input bias current, dual-phase At rising threshold -200 -166 -120 µA
VCS_DPh CS current-limit rising threshold, dual-phase -0.22 -0.2 -0.18 V
VCS_SPh CS current-limit rising threshold, single-phase PHB = 6 V -0.183 -0.166 -0.149 V
VCS_RST CS current-limit reset falling threshold -0.025 –0.015 -0.002 V
tCS_DEL CS current-limit response time From CS exceeding threshold−0.05 V to GDx dropping 10% 60 100 ns
tCS_BLNK CS blanking time From GDx rising and falling edges 100 ns
VINAC INPUT
IVINAC VINAC input bias current, above brownout VINAC = 2 V -0.5 0 0.5 µA
VBOTHR VINAC brownout threshold 1.33 1.45 1.6 V
tBODLY VINAC brownout filter time VINAC below the brownout threshold for the brownout filter time 500 640 810 ms
tBORST VINAC brownout reset time VINAC above the brownout threshold for the brownout reset time after Brown out event 300 450 600 ms
IBOHYS VINAC brownout hysteresis current VINAC = 1 V for > tBODLY 1.6 1.95 2.25 µA
VDODET VINAC dropout detection threshold VINAC falling 0.310 0.35 0.38 V
tDODLY VINAC dropout filter time VINAC below the dropout detection threshold for the dropout filter time 3.5 5 7 ms
VDOCLR VINAC dropout clear threshold VINAC rising 0.67 0.71 0.75 V
PULSE-WIDTH MODULATOR
KTL On-time factor, two phases operating, low VINAC_PK VINAC=1.6V, VCOMP=4V(2) 3.0 4.15 5.3 µs/V
KTH On-time factor, two phases operating, high VINAC_PK VINAC= 5V, VCOMP = 4V(2) 0.36 0.43 0.5 µs/V
KTSL On-time factor, single-phase operating, low VINAC_PK VINAC=1.6V, VCOMP = 1.5V, PHB = 2V(2) 6.1 8.3 10.5 µs/V
KTSH On-time factor, single-phase operating, high VINAC_PK VINAC= 5V, VCOMP = 1.5V, PHB=2V(2) 0.73 0.87 1.01 µs/V
tZCC_I Zero-crossing distortion correction additional on time COMP = 0.5 V, VINAC = 0.1 V 15 23.6 32.2 µs
tZCC_II Zero-crossing distortion correction additional on time COMP = 0.5 V, VINAC = 1.6 V 0.7 1.1 1.5 µs
tMIN Minimum Switching period RTSET = 133 kΩ, VCOMP = 0.3, VINAC = 3 V(2) 1.9 2.7 3.5 µs
tSTART PWM restart time ZCDA = ZCDB = 2 V(3) 160 210 265 µs
tONMAX_L Maximum FET on time at low VINAC VSENSE = 5.8 V, VINAC=1.6V 15.1 20.4 26.2 µs
tONMAX_H Maximum FET on time at High VINAC VSENSE = 5.8 V, VINAC= 5V 1.5 2 2.4 µs
tONMAX_SL Maximum FET on time at low VINAC, Single Phase operation. VSENSE = 5.8V, VINAC=1.6V, PHB = 6V 11.8 16 20.2 µs
tONMAX_SH Maximum FET on time at hgih VINAC, single phase operation VSENSE = 5.8V, VINAC=5 V, PHB = 6V 1.37 1.66 1.95 µs
ΔtONMAX_AB_L Phase B to phase A on-time matching error VSENSE = 5.8 V, VINAC=1.6V –6 6 %
ΔtONMAX_AB_H Phase B to phase A on-time matching error VSENSE = 5.8 V, VINAC= 5V -6 6 %
ΔVBRST_HYST BRST Hysteresis, COMP voltage rising BRST = 1V, VINAC = 1.5 V 30 50 70 mV
ΔVPHB_HYST PHB Hysteresis COMP voltage rising PHB = 3V, VINAC = 2.5 V 80 150 210 mV
IPHB_RANGE PHB pin sourced current when high input voltage VINAC = 3.75V, PHB = 2V 2 3 4.1 µA
IBRST_RANGE BRST pin sourced current when high input voltage VINAC = 3.75V, BRST = 2V 2 3 4.1 µA
VVINAC_RANGE_THF VINAC range falling threshold PHB = 2V, BRST = 2V 2.95 3.15 3.3 V
ΔVINAC_RANGE VINAC range Hysteresis at rising edge PHB = 2V, BRST=2V 300 350 400 mV
THERMAL SHUTDOWN
TJ Thermal shutdown temperature Temperature rising(4) 160 °C
TJ Thermal restart temperature Temperature falling(4) 140 °C
(1) Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply. If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended. See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.
(2) Gate drive on-time is proportional to (VCOMP – 0.125 V). The on-time proportionality factor, KT, scales linearly with the value of RTSET and is different in two-phase and single-phase modes. The minimum switching period is proportional to RTSET.
(3) An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.
(4) Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating temperature is not specified or assured.