JAJSC34B March   2012  – December 2023 UCC28070A

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Interleaving
      2. 6.3.2  Programming the PWM Frequency and Maximum Duty-Cycle Clamp
      3. 6.3.3  Frequency Dithering (Magnitude and Rate)
      4. 6.3.4  External Clock Synchronization
      5. 6.3.5  Multi-phase Operation
      6. 6.3.6  VSENSE and VINAC Resistor Configuration
      7. 6.3.7  VSENSE and VINAC Open-Circuit Protection
      8. 6.3.8  Current Synthesizer
      9. 6.3.9  Programmable Peak Current Limit
      10. 6.3.10 Linear Multiplier and Quantized Voltage Feed Forward
      11. 6.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
      12. 6.3.12 Voltage Biasing (VCC and VVREF)
      13. 6.3.13 PFC Enable and Disable
      14. 6.3.14 Adaptive Soft Start
      15. 6.3.15 PFC Start-Up Hold Off
      16. 6.3.16 Output Overvoltage Protection (OVP)
      17. 6.3.17 Zero-Power Detection
      18. 6.3.18 Thermal Shutdown
      19. 6.3.19 Current Loop Compensation
      20. 6.3.20 Voltage Loop Compensation
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Current Calculation
        2. 7.2.2.2 Bridge Rectifier
        3. 7.2.2.3 PFC Inductor (L1 and L2)
        4. 7.2.2.4 PFC MOSFETs (M1 and M2)
        5. 7.2.2.5 PFC Diode
        6. 7.2.2.6 PFC Output Capacitor
        7. 7.2.2.7 Current-Loop Feedback Configuration (Sizing of the Current-Transformer Turns-Ratio and Sense Resistor (RS))
        8. 7.2.2.8 Current-Sense Offset and PWM Ramp for Improved Noise Immunity
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Linear Multiplier and Quantized Voltage Feed Forward

The UCC28070A multiplier generates a reference current which represents the desired wave shape and proportional amplitude of the AC input current. This current is converted to a reference voltage signal by the RIMO resistor which is scaled in value to match the voltage of the current-sense signals. The instantaneous multiplier current is dependent upon the rectified, scaled input voltage VVINAC and the voltage-error amplifier output VVAO. VVINAC conveys three pieces of information to the multiplier:

  • The overall wave-shape of the input voltage (typically sinusoidal)
  • The instantaneous input voltage magnitude at any point in the line cycle
  • The rms level of the input voltage.
VVAO represents the total output power of the PFC preregulator.

A major innovation in the UCC28070A multiplier architecture is the internal quantized VRMS feed-forward (QVFF) circuitry, which eliminates the requirement for external filtering of the VINAC signal and the subsequent slow response to transient line variations. A unique circuit algorithm detects the transition of the peak of VVINAC through seven thresholds and generates an equivalent VFF level centered within the 8-QVFF ranges. The boundaries of the ranges expand with increasing VIN to maintain an approximately equal-percentage delta between levels. These 8-QVFF levels are spaced to accommodate the full universal line range of 85VRMS to 265VRMS.

A great benefit of the QVFF architecture is that the fixed kVFF factors eliminate any contribution to distortion of the multiplier output, unlike an externally-filtered VINAC signal which unavoidably contains 2nd-harmonic distortion components. Furthermore, the QVFF algorithm allows for rapid response to both increasing and decreasing changes in input rms voltage so that disturbances transmitted to the PFC output are minimized. 5% hysteresis in the level thresholds help avoid chattering between QVFF levels for VVINAC voltage peaks near a particular threshold or containing mild ringing or distortion. The QVFF architecture requires that the input voltage be largely sinusoidal, and relies on detecting zero-crossings to adjust QVFF downward on decreasing input voltage. Zero-crossings are defined as VVINAC falling below 0.7V for at least 50μs, typically.

Table 6-1 shows the relationship between the various VVINAC peak voltages and the corresponding kVFF terms for the multiplier equation.

Table 6-1 VVINAC Peak Voltages
LEVELVVINAC PEAK VOLTAGEkVFF (V2)VIN PEAK VOLTAGE (1)
82.6V ≤ VVINAC(pk)3.857>345V
72.25V ≤ VVINAC(pk) < 2.6V2.922300V to 345V
61.95V ≤ VVINAC(pk) < 2.25V2.199260V to 300V
51.65V ≤ VVINAC(pk) < 1.95V1.604220V to 260V
41.4V ≤ VVINAC(pk) < 1.65V1.156187V to 220V
31.2V ≤ VVINAC(pk) < 1.4V0.839160V to 187V
21V ≤ VVINAC(pk) < 1.2V0.6133V to 160V
1VVINAC(pk) ≤ 1V0.398<133V
The VIN peak voltage boundary values listed above are calculated based on a 400V PFC output voltage and the use of a matched resistor-divider network (kR = 3V / 400V = 0.0075) on VINAC and VSENSE (as required for current synthesis). When VOUT is designed to be higher or lower than 400V, kR = 3V / VOUT, and the VIN peak voltage boundary values for each QVFF level adjust to VVINAC(pk) / kR.

The multiplier output current IIMO for any line and load condition can thus be determined using Equation 13:

Equation 13. GUID-68E9FA2D-7CF4-43EE-98D8-7DBB31E12AE1-low.gif

Because the kVFF value represents the scaled (VRMS)2 at the center of a level, VVAO adjusts slightly upwards or downwards when VVINAC(pk) is either lower or higher than the center of the QVFF voltage range to compensate for the difference. This is automatically accomplished by the voltage loop control when VIN varies, both within a level and after a transition between levels.

The output of the voltage-error amplifier (VVAO) is clamped at 5V, which represents the maximum PFC output power. This value is used to calculate the maximum reference current at the IMO pin, and sets a limit for the maximum input power allowed (and, as a consequence, limits maximum output power).

Unlike a continuous VFF situation, where maximum input power is a fixed power at any VRMS input, the discrete QVFF levels permit a variation in maximum input power within limited boundaries as the input VRMS varies within each level.

The lowest maximum power limit occurs at the VVINAC voltage of 0.76V, while the highest maximum power limit occurs at the increasing threshold from level-1 to level-2. This pattern repeats at every level transition threshold, considering that decreasing thresholds are 95% of the increasing threshold values. Below VVINAC = 0.76V, PIN is always less than PIN(max), falling linearly to zero with decreasing input voltage.

For example, to design for the lowest maximum power allowable, determine the maximum steady-state (average) output power required of the PFC preregulator and add some additional percentage to account for line drop-out recovery power (to recharge COUT while full load power is drawn) such as 10% or 20% of POUT(max). Then apply the expected efficiency factor to find the lowest maximum input power allowable:

Equation 14. GUID-81D75B1C-5455-463D-BC94-D6EDDD7D1457-low.gif

At the PIN(max) design threshold, VVINAC = 0.76V, hence QVFF = 0.398 and input VAC = 73VRMS (accounting for 2V bridge-rectifier drop) for a nominal 400V output system.

Equation 15. GUID-CA928069-8741-4686-8F70-B2B1A51E4693-low.gif
Equation 16. GUID-6AC06D45-3C48-4335-80E4-59157C4A1CE1-low.gif

This IIN(pk) value represents the combined average current through the boost inductors at the peak of the line voltage. Each inductor current is detected and scaled by a current-sense transformer (CT). Assuming equal currents through each interleaved phase, the signal voltage at each current sense input pin (CSA and CSB) is developed across a sense resistor selected to generate approximately 3V based on ½ IIN(pk) × RS / NCT, where RS is the current sense resistor and NCT is the CT turns-ratio.

IIMO is then calculated at that same lowest maximum-power point, as:

Equation 17. GUID-67C6145D-769C-42A3-8512-FD38E81B78A3-low.gif

RIMO is selected such that:

Equation 18. GUID-4A601AE7-39D3-44CD-BE6A-27B3D542D0E9-low.gif

Therefore:

Equation 19. GUID-097AC01B-388B-464D-BAF8-E3DE194F77F6-low.gif

At the increasing side of the level-1 to level-2 threshold, note that the IMO current would allow higher input currents at low-line:

Equation 20. GUID-CFA40989-3079-41F0-B792-6B6068A7440D-low.gif

However, this current may easily be limited by the programmable peak current limiting (PKLMT) feature of the UCC28070A if required by the power stage design.

The same procedure can be used to find the lowest and highest input power limits at each of the QVFF level transition thresholds. At higher line voltages, where the average current with inductor ripple is traditionally below the PKLMT threshold, the full variation of maximum input power is seen, but the input currents are inherently below the maximum acceptable current levels of the power stage.

The performance of the multiplier in the UCC28070A has been significantly enhanced when compared to previous generation PFC controllers, with high linearity and accuracy over most of the input ranges. The accuracy is at its worst as VVAO approaches 1V because the error of the (VVAO – 1) subtraction increases and begins to distort the IMO reference current to a greater degree.