The UCC28070A operates within a V_CC bias supply range of 10V to 21V. An undervoltage lockout (UVLO) threshold prevents the PFC from activating until V_CC > 10.2V, and 1V of hysteresis assures reliable start-up from a possibly low-compliance bias source. An internal 25V Zener-like clamp on the VCC pin is intended only to protect the device from brief energy-limited surges from the bias supply, and must not be used as a regulator with a current-limited source.

At minimum, a 0.1μF ceramic bypass capacitor must be applied from VCC to GND close to the device pins to provide local filtering of the bias supply. Larger values may be required depending on I_CC peak current magnitudes and durations to minimize ripple voltage on VCC.

To provide a smooth transition out of UVLO and to make the 6V voltage reference available as early as possible, the output from VREF is enabled when V_CC exceeds 8V typically.

The VREF circuitry is designed to provide the biasing of all internal control circuits and for limited use externally. At minimum, a 22nF ceramic bypass capacitor must be applied from VREF to GND close to the device pins to ensure stability of the circuit. External load current on the VREF pin must be limited to less than 2mA, or degraded regulation may result.