JAJSC34B March   2012  – December 2023 UCC28070A

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Interleaving
      2. 6.3.2  Programming the PWM Frequency and Maximum Duty-Cycle Clamp
      3. 6.3.3  Frequency Dithering (Magnitude and Rate)
      4. 6.3.4  External Clock Synchronization
      5. 6.3.5  Multi-phase Operation
      6. 6.3.6  VSENSE and VINAC Resistor Configuration
      7. 6.3.7  VSENSE and VINAC Open-Circuit Protection
      8. 6.3.8  Current Synthesizer
      9. 6.3.9  Programmable Peak Current Limit
      10. 6.3.10 Linear Multiplier and Quantized Voltage Feed Forward
      11. 6.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
      12. 6.3.12 Voltage Biasing (VCC and VVREF)
      13. 6.3.13 PFC Enable and Disable
      14. 6.3.14 Adaptive Soft Start
      15. 6.3.15 PFC Start-Up Hold Off
      16. 6.3.16 Output Overvoltage Protection (OVP)
      17. 6.3.17 Zero-Power Detection
      18. 6.3.18 Thermal Shutdown
      19. 6.3.19 Current Loop Compensation
      20. 6.3.20 Voltage Loop Compensation
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Current Calculation
        2. 7.2.2.2 Bridge Rectifier
        3. 7.2.2.3 PFC Inductor (L1 and L2)
        4. 7.2.2.4 PFC MOSFETs (M1 and M2)
        5. 7.2.2.5 PFC Diode
        6. 7.2.2.6 PFC Output Capacitor
        7. 7.2.2.7 Current-Loop Feedback Configuration (Sizing of the Current-Transformer Turns-Ratio and Sense Resistor (RS))
        8. 7.2.2.8 Current-Sense Offset and PWM Ramp for Improved Noise Immunity
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

PFC Inductor (L1 and L2)

The selection of the PFC inductor value is usually based on a number of different considerations. Cost, core size, EMI filter, and inductor ripple current are some of the factors that have an influence. In previous versions of this data sheet, the design method to choose the inductor targetted the peak to peak inductor ripple current (ΔIL) at the minimum input voltage to have the same amplitude as the peak of AC-line current in each phase. The line current flows equally in the two phases so ΔIL is half Iin_pk calculated in Equation 38. That method worked well for relatively low minimum input voltages, but was found to generate excessively low inductances for minimum inputs with peak voltages near ½ VOUT.

A new method of calculating boost inductance is presented in this datasheet where low input-current distortion is the main design criterion. In recent years, low distortion at lighter loads and higher input voltages has become a major design requirement in many applications. In a CCM-Boost-PFC, the total harmonic distortion of the input current (THDi) increases greatly when the inductor current operates in DCM over a significant portion of the input AC-line cycle. To maintain low THDi at any given line and load point, it is necessary to maintain CCM in the boost inductors at that operating point. Since a PFC converter is intended to present an equivalent or emulated resistance Re to the AC line, it can be shown [5] that inductor current operates in CCM over the entire line cycle when:

Equation 41. Re<2×LBTPWM,  where Re=Vrms2PIN  and TPWM=1fPWM 

By rearranging terms and substituting, the minimum boost inductance necessary to maintain CCM is calculated as:

Equation 42. L 1 = L 2 = L B V r m s _ C C M ( m a x ) 2 2 × P O _ C C M ( m i n ) / η × f P W M

where

  • Vrms_CCM(max) is the highest rms input voltage at which CCM operation is to be maintained
  • PO_CCM(min) is the lowest output power level per inductor where CCM is to be maintained
  • η is the expected conversion efficiency at PO_CCM(min) and Vrms_CCM(max)

Lower values of boost inductance than that calculated by Equation 42 can be used for PFC, but THDi will increase as the amount of DCM increases in the line cycle. To match the previous data sheet inductor selection, it can be seen that for CCM operation at 100Vrms input, 150W per phase, 95 % efficiency, and 200kHz PWM switching frequency, LB must be ≥ 158.333µH.
Select L1 = L2 = 160µH.

Given that inductance, ΔIL at the peak of low-line can be calculated as follows:

Equation 43. IL=VOUT-2×VAC_minLB×2×VAC_minVOUT×TPWM= 385 V-120 V160 μH×120 V385 V×5 μs=~2.57 A

Then, the peak current in each boost inductor is approximately:

Equation 44. IL_pk=Iin_pk2+IL2=5.1 A2+2.57 A2=~3.8 A

The basic inductor specifications for this application example are:

  • Inductance: 160µH
  • Peak current: 4A