SGLS245E May   2020  – May 2020 UCC2813-0-Q1 , UCC2813-1-Q1 , UCC2813-2-Q1 , UCC2813-3-Q1 , UCC2813-4-Q1 , UCC2813-5-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Descriptions
        1. 8.3.1.1 COMP
        2. 8.3.1.2 CS
        3. 8.3.1.3 FB
        4. 8.3.1.4 GND
        5. 8.3.1.5 OUT
        6. 8.3.1.6 RC
        7. 8.3.1.7 REF
        8. 8.3.1.8 VCC
      2. 8.3.2  Undervoltage Lockout (UVLO)
      3. 8.3.3  Self-Biasing, Active Low Output
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Oscillator
      6. 8.3.6  Synchronization
      7. 8.3.7  PWM Generator
      8. 8.3.8  Minimum Off-Time Adjustment (Dead-Time Control)
      9. 8.3.9  Leading Edge Blanking
      10. 8.3.10 Minimum Pulse Width
      11. 8.3.11 Current Limiting
      12. 8.3.12 Overcurrent Protection and Full-Cycle Restart
      13. 8.3.13 Soft Start
      14. 8.3.14 Slope Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
      3. 8.4.3 Soft-Start Mode
      4. 8.4.4 Fault Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Bulk Capacitor Calculation
        2. 9.2.2.2  Transformer Design
        3. 9.2.2.3  MOSFET and Output Diode Selection
        4. 9.2.2.4  Output Capacitor Calculation
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  REF Bypass Capacitor
        8. 9.2.2.8  RT and CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation Procedure
          1. 9.2.2.10.1 Power Stage Gain, Zeroes, and Poles
          2. 9.2.2.10.2 Compensating the Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

8.4.2 UVLO Mode

During the system start-up, VVCC voltage starts to rise from 0 V. Before the VCC voltage reaches its corresponding turn-on threshold, the device operates in UVLO mode. In this mode, REF pin voltage is not generated. When VVCC is above 1 V and below the turnon threshold, the REF pin is actively pulled low through a 5-kΩ resistor. This way, VREF can be used as a logic signal to indicate UVLO mode.