JAJS121G September   2003  – April 2017 UCC28220 , UCC28221

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD
      2. 8.3.2 Reference
      3. 8.3.3 Oscillator Operation and Maximum Duty Cycle Setpoint
      4. 8.3.4 Soft Start
      5. 8.3.5 Current Sense
      6. 8.3.6 Output Drivers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Line Overvoltage and Undervoltage
      2. 8.4.2 Start-Up JFET Section
      3. 8.4.3 Slope Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Overvoltage Protection and Undervoltage Lockout
        2. 9.2.2.2 Peak Current Limit
        3. 9.2.2.3 Current Sense Transformer Reset Resistor (T1 and T2)
        4. 9.2.2.4 Oscillator and Maximum Duty Cycle Clamp
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCC28220 control device from Texas Instruments is used in a dual-interleaved, forward converter that enables the power supply designer to reduce output current ripple and reduce magnetic size per power stage allowing for improved transient response. The UCC28220 is a dual-interleaved PWM controller with programmable maximum duty cycle per channel up to 90% for interleaved forward and interleaved flyback designs.

9.2 Typical Application

UCC28220 UCC28221 interleaved_boost_app_slus544.gif Figure 21. Interleaved Boost Application Circuit Using the UCC28220

9.2.1 Design Requirements

Table 1 lists the design parameters for the interleaved boost application circuit.

Table 1. Design Parameters

PARAMETER MIN TYP MAX UNIT
VIN 85 110 or 230 265 V RMS
VOUT 374 390 425 V
VRIPPLE — — 30 V
Current THD at 350 W — — 10%
PF at 350 W 0.95 — —
Full load efficiency 90% — —
fS — 100 — kHz
Holdup requirements, tHOLD — — 20 ms
fLINE 47 50 60 Hz

9.2.2 Detailed Design Procedure

9.2.2.1 Overvoltage Protection and Undervoltage Lockout

The OVP function and undervoltage lockout (UVLO) were handled by the UCC28220. It is a simple comparator that monitors the boost voltage. The OVP for this design was set to 425 V and UVLO was set to 108 V. The preregulator does not start switching until VOUT reaches 108 V.

9.2.2.2 Peak Current Limit

Peak current limit is set by the maximum control voltage (VC) at the input of the UCC28220’s PWM comparator with Equation 10 through Equation 12. Where a is the current sense transformer turns ratio of T1 and T2. The peak current limit trip point was set for 130% of the nominal peak current to protect the boost FETs.

Equation 10. UCC28220 UCC28221 equation_44_slus544f.gif
Equation 11. UCC28220 UCC28221 equation_45_slus544f.gif

VC = 1.8, VCTRL was set to a maximum of 3 V to protect the UCC28220 CTRL pin.

Equation 12. UCC28220 UCC28221 equation_47_slus544f.gif

Equation 12 considers slope compensation that is added later.

The peak current of the FET during power up is 2 times IPEAK under normal operation as calculated with Equation 13. This is due to the excessive slope compensation that is required for stability.

Equation 13. UCC28220 UCC28221 equation_48_slus544f.gif

9.2.2.3 Current Sense Transformer Reset Resistor (T1 and T2)

Equation 14. UCC28220 UCC28221 equation_49_slus544f.gif

9.2.2.4 Oscillator and Maximum Duty Cycle Clamp

The UCC28220’s oscillator and maximum duty cycle clamp are setup through resistor RCHG and discharge. The desired duty cycle clamp (DMAX) was set at 0.9 to stop the current sense transformers from saturating.

Equation 15. UCC28220 UCC28221 equation_50_slus544f.gif

Equation 15 is UCC28220's oscillator constant.

Equation 16. UCC28220 UCC28221 equation_51_slus544f.gif

Equation 16 is UCC28220's internal oscillator frequency.

Equation 17. UCC28220 UCC28221 equation_51_slus544f.gif

Equation 17 is the internal duty cycle clamp.

Equation 18. UCC28220 UCC28221 equation_53_slus544f.gif
Equation 19. UCC28220 UCC28221 equation_54_slus544f.gif

9.2.3 Application Curves

UCC28220 UCC28221 figure_11_slus544.gif
POUT = 350 W
Figure 22. Output Ripple Voltage
UCC28220 UCC28221 figure_17_slus544.gif
Line transients at 350-W load
VIN stepped from 240 V to 120 V to 240 V
Figure 23. Line Dropout at Full Load