JAJS121G September   2003  – April 2017 UCC28220 , UCC28221

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD
      2. 8.3.2 Reference
      3. 8.3.3 Oscillator Operation and Maximum Duty Cycle Setpoint
      4. 8.3.4 Soft Start
      5. 8.3.5 Current Sense
      6. 8.3.6 Output Drivers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Line Overvoltage and Undervoltage
      2. 8.4.2 Start-Up JFET Section
      3. 8.4.3 Slope Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Overvoltage Protection and Undervoltage Lockout
        2. 9.2.2.2 Peak Current Limit
        3. 9.2.2.3 Current Sense Transformer Reset Resistor (T1 and T2)
        4. 9.2.2.4 Oscillator and Maximum Duty Cycle Clamp
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

D or PW Package
16-Pin SOIC or TSSOP
Top View
UCC28220 UCC28221 SOIC_16_slus544.gif
PW Package
20-Pin TSSOP
Top View
UCC28220 UCC28221 TSSOP_20_slus544.gif

Pin Functions

PIN I/O DESCRIPTION
NAME SOIC,
TSSOP (16)		 TSSOP (20)
CHG 10 13 I Sets oscillator charge current: A resistor from this pin to GND sets up the charging current of the internal CT capacitor used in the oscillator. This resistor, in conjunction with the resistor on the DISCHG pin is used to set up the operating frequency and maximum duty cycle. Under normal operation the dc voltage on this pin is 2.5 V.
CS1 4 5 I Channel 1 current sense input: These 2 pins are the current sense inputs to the device. The signals are internally level shifted by 0.5 V before the signal gets to the PWM comparator. Internally the slope compensation ramp is added to this signal. The linear operating range on this input is 0 to 1.5 V. Also, this pin gets pulled to ground each time its respective output goes low (that is: OUT1 and OUT2).
CS2 6 7 I Channel 2 current sense input: These 2 pins are the current sense inputs to the device. The signals are internally level shifted by 0.5 V before the signal gets to the PWM comparator. Internally the slope compensation ramp is added to this signal. The linear operating range on this input is 0 to 1.5 V. Also, this pin gets pulled to ground each time its respective output goes low (that is: OUT1 and OUT2).
CTRL 8 9 I Feedback control input:
DISCHG 9 12 I Sets oscillator discharge current: A resistor from this pin to GND sets up the discharge current of the internal CT capacitor used in the oscillator. This resistor, in conjunction with the resistor on the CHG pin is used to set up the operating frequency and maximum duty cycle. Under normal operation the dc voltage on this pin is 2.5 V.
GND 11 14 — Device ground
LINEHYS 2 3 I Sets line comparator hysteresis: This pin is controlled by both the LINEOV and LINEUV pins. It is used to control the hysteresis values for both the over and under voltage line detectors.
LINEOV 1 2 I Input for line over voltage comparator: This pin is connected to a comparator and used to monitor the line voltage for an over voltage condition. The typical threshold is 1.26 V.
LINEUV 15 18 I Input for line under voltage comparator: This pin is connected to a comparator and used to monitor the line voltage for an under voltage condition. The typical threshold is 1.26 V.
N/C 16 1, 10, 11, 19 — No connection
OUT1 13 16 O PWM output from channel 1: These output buffers are intended to interface with high current MOSFET drivers. The output drive capability is approximately 33 mA and has an output impedance of 100 Ω. The outputs swing between GND and REF.
OUT2 12 15 O PWM output from channel 2: These output buffers are intended to interface with high current MOSFET drivers. The output drive capability is approximately 33 mA and has an output impedance of 100 Ω. The outputs swing between GND and REF.
REF 14 17 O Reference voltage output: REF is a 3.3-V output used primarily as a source for the output buffers and other internal circuits. It is protected from accidental shorts to ground. For improved noise immunity, TI recommends the reference pin be bypassed with a minimum of 0.1 µF of capacitance to GND.
SLOPE 5 6 I Sets slope compensation: This pin sets up a current used for the slope compensation ramp. A resistor to ground sets up a current, which is internally divided by 25 and then applied to an internal 10-pF capacitor. Under normal operation th dc voltage on this pin is 2.5 V.
SS 7 8 I Soft-start input: A capacitor to ground sets up the soft-start time for the open loop soft-start function. The source and sink current from this pin is equal to 3/7th of the oscillator charge current set by the resistor on the CHG pin. The soft start capacitor is held low during UVLO and during a Line OV or UV condition. Once an OV or UV fault occurs, the soft-start capacitor is discharged by a current equal to its charging current. The capacitor does NOT quickly discharge during faults. In this way, the controller has the ability to recover quickly from very short line transients. This pin can also be used as an Enable/Disable function.
VDD 3 4 I Device supply input: This is used to supply power to the device, monitoring this pin is a the UVLO circuit. This is used to insure glitch-free startup operation. Until VDD reaches its UVLO threshold, it remains in a low power mode, drawing approximately 150 µA of current and forcing pins, SS, CS1, CS2, OUT1, and OUT2 to logic 0 states. If the VDD falls below 8 V after reaching turnon, it goes back into this low power state. In the case of the UCC28221, the UVLO threshold is 13 V. It is 10 V for the UCC28220. Both versions have a turnoff threshold of 8 V.
VIN — 20 I High voltage start-up input: This pin has an internal high voltage JFET used for startup. The drain is connected to VIN, while its’ source is connected to VDD. During startup, this JFET delivers 12 mA typically with a minimum of 4 mA to VDD, which in turn, charges up the VDD bypass capacitor. When VDD gets to 13 V, the JFET is turned off.