JAJSHT2C august   2019  – december 2020 UCC28740-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Revision History
  7. 6 Revision History
  8. 7 Pin Configuration and Functions
    1. 7.1 Pin Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Detailed Pin Description
      2. 9.3.2 Valley-Switching and Valley-Skipping
      3. 9.3.3 Startup Operation
      4. 9.3.4 Fault Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      2. 9.4.2 Primary-Side Constant-Current (CC) Regulation
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 High Voltage Applications
    3. 10.3 Typical Application
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure
        1. 10.3.2.1  Custom Design With WEBENCH® Tools
        2. 10.3.2.2  Standby Power Estimate and No-Load Switching Frequency
        3. 10.3.2.3  Input Bulk Capacitance and Minimum Bulk Voltage
        4. 10.3.2.4  38
        5. 10.3.2.5  Transformer Turns-Ratio, Inductance, Primary Peak Current
        6. 10.3.2.6  Transformer Parameter Verification
        7. 10.3.2.7  VS Resistor Divider, Line Compensation
        8. 10.3.2.8  Output Capacitance
        9. 10.3.2.9  VDD Capacitance, CVDD
        10. 10.3.2.10 Feedback Network Biasing
      3. 10.3.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 VDD Pin
      2. 12.1.2 VS Pin
      3. 12.1.3 FB Pin
      4. 12.1.4 GND Pin
      5. 12.1.5 CS Pin
      6. 12.1.6 DRV Pin
      7. 12.1.7 HV Pin
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Custom Design With WEBENCH® Tools
      2. 13.1.2 Device Nomenclature
        1. 13.1.2.1  Capacitance Terms in Farads
        2. 13.1.2.2  Duty Cycle Terms
        3. 13.1.2.3  Frequency Terms in Hertz
        4. 13.1.2.4  Current Terms in Amperes
        5. 13.1.2.5  Current and Voltage Scaling Terms
        6. 13.1.2.6  Transformer Terms
        7. 13.1.2.7  Power Terms in Watts
        8. 13.1.2.8  Resistance Terms in Ohms
        9. 13.1.2.9  Timing Terms in Seconds
        10. 13.1.2.10 Voltage Terms in Volts
        11. 13.1.2.11 AC Voltage Terms in VRMS
        12. 13.1.2.12 Efficiency Terms
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
  15.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.3 Application Curves

The transient response shown in Figure 10-3 was taken with a 115 VAC, 60 Hz input voltage and a load transition from 0 A to full load. Channel 1 is the load current on a scale of 1 A per division, channel 4 is the otutput voltage on a scale of 1 V per division. The cursor shows the minimum acceptable voltage limit, 4.30 V, under transient conditions. Also note that the output waveform was taken with the probe on TP5 with the ground referenced to TP4 but not using the tip and barrel technique accounting for the high frequency noise seen on the waveform.

The typical switching waveform can be seen in Figure 10-4. Channel 1 shows the VS pin at 2 V per division and channel 2 shows the MOSFET drain to source voltage at 100 V per division. The scan was taken at 1.8-A load, 115-VAC, 60-Hz input voltage. At this operating point, the switching frequency is dithering between 58.8 kHz and 52.6 kHz due to valley skipping.

The UCC28740-Q1 controller employs a unique control mechanism to help with EMI compliance. As shown in Figure 10-5, the DRV pin, shown as channel 3, drives the gate of the MOSFET with a sequence of pulses in which there will be two longer pulses, two medium pulses, and two shorter pulses at any operating point starting with the amplitude modulation mode. The EMI dithering is not enabled at light load. Figure x shows the result of these varying pulse widths on the CS signal, shown on channel 4. The longer pulses result in a peak current threshold of 808 mV, the medium length pulses are shown measured at 780 mV, and the shorter pulses measure a threshold voltage of 752 mV. This dithering adds to the frequency jitter caused by valley skipping and results in a spread spectrum for better EMI compliance.

GUID-1276EBA6-B374-46BF-8562-353811CE3892-low.png
115 VAC, 60 Hz0 A to 2 A
CH 1 = Load Current, 1 A/DIV
CH 4 = VOUT, cursor shows minimum limit
Figure 10-3 Transient Response
GUID-8430F0C2-BAE7-4CEA-BFE4-1FB2A1F5E3D9-low.pngFigure 10-5 EMI Dithering
GUID-625B00DC-E16A-40D5-9167-22510244CA78-low.gifFigure 10-7 Average Efficiency
GUID-4992B090-36BC-4C1D-AFC6-D14140EA4035-low.gifFigure 10-9 VOUT vs. IOUT
GUID-CD96E6CB-E67B-404B-AC8F-846F9A999870-low.gif
VIN = 115 VACIOUT = 2 A
Figure 10-11 Bode Plot
GUID-226A1CB2-CE45-4C71-BEE5-BE4BCA44BC1C-low.png
CH 1 = VSCH 2 = VDS
IOUT = 1.8 AVIN = 115 VAC, 60 Hz
Figure 10-4 Switching Waveform
GUID-2448257D-0A7A-48B0-8276-715BC485B58C-low.gif
Figure 10-6 Efficiency
GUID-D2C7F6FE-2571-495A-B51E-F36D769A5EC1-low.gifFigure 10-8 No Load Power Consumption
GUID-111F909A-A21F-4736-87CF-2851477298A4-low.gifFigure 10-10 Control Law