JAJSHT2C august   2019  – december 2020 UCC28740-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Revision History
  7. 6 Revision History
  8. 7 Pin Configuration and Functions
    1. 7.1 Pin Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Detailed Pin Description
      2. 9.3.2 Valley-Switching and Valley-Skipping
      3. 9.3.3 Startup Operation
      4. 9.3.4 Fault Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      2. 9.4.2 Primary-Side Constant-Current (CC) Regulation
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 High Voltage Applications
    3. 10.3 Typical Application
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure
        1. 10.3.2.1  Custom Design With WEBENCH® Tools
        2. 10.3.2.2  Standby Power Estimate and No-Load Switching Frequency
        3. 10.3.2.3  Input Bulk Capacitance and Minimum Bulk Voltage
        4. 10.3.2.4  38
        5. 10.3.2.5  Transformer Turns-Ratio, Inductance, Primary Peak Current
        6. 10.3.2.6  Transformer Parameter Verification
        7. 10.3.2.7  VS Resistor Divider, Line Compensation
        8. 10.3.2.8  Output Capacitance
        9. 10.3.2.9  VDD Capacitance, CVDD
        10. 10.3.2.10 Feedback Network Biasing
      3. 10.3.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 VDD Pin
      2. 12.1.2 VS Pin
      3. 12.1.3 FB Pin
      4. 12.1.4 GND Pin
      5. 12.1.5 CS Pin
      6. 12.1.6 DRV Pin
      7. 12.1.7 HV Pin
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Custom Design With WEBENCH® Tools
      2. 13.1.2 Device Nomenclature
        1. 13.1.2.1  Capacitance Terms in Farads
        2. 13.1.2.2  Duty Cycle Terms
        3. 13.1.2.3  Frequency Terms in Hertz
        4. 13.1.2.4  Current Terms in Amperes
        5. 13.1.2.5  Current and Voltage Scaling Terms
        6. 13.1.2.6  Transformer Terms
        7. 13.1.2.7  Power Terms in Watts
        8. 13.1.2.8  Resistance Terms in Ohms
        9. 13.1.2.9  Timing Terms in Seconds
        10. 13.1.2.10 Voltage Terms in Volts
        11. 13.1.2.11 AC Voltage Terms in VRMS
        12. 13.1.2.12 Efficiency Terms
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
  15.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.2.3 Input Bulk Capacitance and Minimum Bulk Voltage

Determine the minimum voltage on the input bulk capacitance, CB1 and CB2 total, in order to determine the maximum Np-to-Ns turns-ratio of the transformer. The input power of the converter based on target full-load efficiency, the minimum input RMS voltage, and the minimum AC input frequency determine the input capacitance requirement.

Maximum input power is determined based on IOCC, VOCV, VCBC (if used), and the full-load conversion-efficiency target.

Equation 10. GUID-1C849915-D75A-4FEF-8585-B42A77A1BED7-low.gif

Equation 11 provides an accurate solution for the total input capacitance based on a target minimum bulk-capacitor voltage. Alternatively, to target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance value.

Equation 11. GUID-D12336B1-6492-4716-9F33-3027DEDD0EFD-low.gif