JAJSHT2C august   2019  – december 2020 UCC28740-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Revision History
  7. 6 Revision History
  8. 7 Pin Configuration and Functions
    1. 7.1 Pin Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Detailed Pin Description
      2. 9.3.2 Valley-Switching and Valley-Skipping
      3. 9.3.3 Startup Operation
      4. 9.3.4 Fault Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      2. 9.4.2 Primary-Side Constant-Current (CC) Regulation
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 High Voltage Applications
    3. 10.3 Typical Application
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure
        1. 10.3.2.1  Custom Design With WEBENCH® Tools
        2. 10.3.2.2  Standby Power Estimate and No-Load Switching Frequency
        3. 10.3.2.3  Input Bulk Capacitance and Minimum Bulk Voltage
        4. 10.3.2.4  38
        5. 10.3.2.5  Transformer Turns-Ratio, Inductance, Primary Peak Current
        6. 10.3.2.6  Transformer Parameter Verification
        7. 10.3.2.7  VS Resistor Divider, Line Compensation
        8. 10.3.2.8  Output Capacitance
        9. 10.3.2.9  VDD Capacitance, CVDD
        10. 10.3.2.10 Feedback Network Biasing
      3. 10.3.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 VDD Pin
      2. 12.1.2 VS Pin
      3. 12.1.3 FB Pin
      4. 12.1.4 GND Pin
      5. 12.1.5 CS Pin
      6. 12.1.6 DRV Pin
      7. 12.1.7 HV Pin
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Custom Design With WEBENCH® Tools
      2. 13.1.2 Device Nomenclature
        1. 13.1.2.1  Capacitance Terms in Farads
        2. 13.1.2.2  Duty Cycle Terms
        3. 13.1.2.3  Frequency Terms in Hertz
        4. 13.1.2.4  Current Terms in Amperes
        5. 13.1.2.5  Current and Voltage Scaling Terms
        6. 13.1.2.6  Transformer Terms
        7. 13.1.2.7  Power Terms in Watts
        8. 13.1.2.8  Resistance Terms in Ohms
        9. 13.1.2.9  Timing Terms in Seconds
        10. 13.1.2.10 Voltage Terms in Volts
        11. 13.1.2.11 AC Voltage Terms in VRMS
        12. 13.1.2.12 Efficiency Terms
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
  15.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

over operating free-air temperature range, VVDD = 25 V, HV = open, VFB = 0 V, VVS = 4 V, TA = –40°C to +125°C, TJ = TA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HIGH-VOLTAGE START UP
IHV Start-up current out of VDD VHV = 100 V, VVDD = 0 V, start state 100 250 500 µA
VHV = 30 V, VVDD = VVDD(on) – 0.5 V, start state 130 410
IHVLKG25 Leakage current at HV VHV = 400 V, run state, TJ = 25°C 0.01 0.5 µA
BIAS SUPPLY INPUT
IRUN Supply current, run IDRV = 0, run state 2 2.65 mA
IWAIT Supply current, wait IDRV = 0, wait state 95 125 µA
ISTART Supply current, start IDRV = 0, VVDD = 18 V, start state, IHV = 0 18 30 µA
IFAULT Supply current, fault IDRV = 0, fault state 95 130 µA
UNDERVOLTAGE LOCKOUT
VVDD(on) VDD turnon threshold VVDD low to high 19 21 23 V
VVDD(off) VDD turnoff threshold VVDD high to low 7.35 7.75 8.15 V
VS INPUT
VVSNC Negative clamp level IVSLS = –300 µA, volts below ground 190 250 325 mV
IVSB Input bias current VVS = 4 V –0.25 0 0.25 µA
FB INPUT
IFBMAX Full-range input current fSW = fSW(min) 16 23 30 µA
VFBMAX Input voltage at full range IFB = 25 µA, TJ = 25°C 0.75 0.88 1 V
RFB FB-input resistance, linearized ΔIFB = 20 µA, centered at IFB = 15 µA, TJ = 25°C 10 14 18 kΩ
CS INPUT
VCST(max) Maximum CS threshold voltage IFB = 0 µA(1) 738 773 810 mV
VCST(min) Minimum CS threshold voltage IFB = 35 µA(1) 170 194 215 mV
KAM AM-control ratio VCST(max) / VCST(min) 3.6 4 4.45 V/V
VCCR Constant-current regulation factor 318 330 343 mV
KLC Line-compensation current ratio IVSLS = –300 µA, IVSLS / current out of CS pin 24 25 28.6 A/A
tCSLEB Leading-edge blanking time DRV output duration, VCS = 1 V 180 230 280 ns
DRIVERS
IDRS DRV source current VDRV = 8 V, VVDD = 9 V 20 25 mA
RDRVLS DRV low-side drive resistance IDRV = 10 mA 6 12 Ω
VDRCL DRV clamp voltage VVDD = 35 V 14 16 V
RDRVSS DRV pulldown in start-state 150 190 230 kΩ
PROTECTION
VOVP Overvoltage threshold At VS input, TJ = 25°C(2) 4.52 4.6 4.74 V
VOCP Overcurrent threshold At CS input 1.4 1.5 1.6 V
IVSL(run) VS line-sense run current Current out of VS pin increasing 190 225 275 µA
IVSL(stop) VS line-sense stop current Current out of VS pin decreasing 70 80 100 µA
KVSL VS line sense ratio IVSL(run) / IVSL(stop) 2.45 2.8 3.05 A/A
TJ(stop) Thermal-shutdown temperature Internal junction temperature 165 °C
(1) This device automatically varies the control frequency and current sense thresholds to improve EMI performance. These threshold voltages and frequency limits represent average levels.
(2) The overvoltage threshold level at VS decreases with increasing temperature by 0.8 mV/°C. This compensation is included to reduce the power-supply output overvoltage detection variance over temperature.