JAJSOG3 December   2023 UCC28750

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Descriptions
      1. 7.3.1 VDD - Input Bias
      2. 7.3.2 DRV - Gate Drive Out
      3. 7.3.3 CS - Current Sensing
      4. 7.3.4 FB - Feedback
      5. 7.3.5 FLT - Fault
      6. 7.3.6 GND - Ground Return
    4. 7.4 Feature Description
      1. 7.4.1 Soft Start
      2. 7.4.2 Control Law
      3. 7.4.3 Frequency Dithering
      4. 7.4.4 Fault Protections
        1. 7.4.4.1 VDD Overvoltage and Undervoltage Lockout
        2. 7.4.4.2 Internal Overtemperature Protection
        3. 7.4.4.3 Output Overpower Protection
        4. 7.4.4.4 Output Short-Circuit Protection
        5. 7.4.4.5 FLT Pin Protections
      5. 7.4.5 Slope Compensation
    5. 7.5 Device Functional Modes
      1. 7.5.1 Off
      2. 7.5.2 Startup
      3. 7.5.3 On
      4. 7.5.4 Fault
      5. 7.5.5 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Bulk Capacitance with Minimum Bulk Voltage
        2. 8.2.3.2 Transformer Turns Ratio and Inductance
        3. 8.2.3.3 Current Sense and Slope Compensation Network
        4. 8.2.3.4 Output Capacitors
        5. 8.2.3.5 VDD Capacitance, CVDD
      4. 8.2.4 Application Performance Plots
        1. 8.2.4.1 Startup
        2. 8.2.4.2 Load Transients
        3. 8.2.4.3 Q1 Drain Voltage Evaluation
      5. 8.2.5 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
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発注情報

5 Pin Configuration and Functions

GUID-20230124-SS0I-KMGJ-FHLR-GGJDDVDLSL8J-low.svg Figure 5-1 Top-view of DBV package (6 pins)
Table 5-1 Pin Descriptions
PINTYPE(1)DESCRIPTION
NAMENO.
GND 1 G Ground return for the controller. Connect this pin to the primary-side ground of the converter using a low-impedance path.
FB 2 I Voltage feedback pin with internal DC bias. Typically, connect this pin to the collector of an opto-coupler device to provide isolated voltage feedback from the secondary side of the converter.
FLT 3 I Fault sensing pin. Implement over-temperature protection by connecting an NTC resistor between this pin and GND. Connecting a resistor or Zener diode from a rectified auxiliary winding voltage can also implement output voltage overvoltage protection. Implement brownout detection by using a resistor divider from the bulk voltage to the FLT pin. Pulling this pin below the disable threshold disables switching operation.
CS 4 I Current-sense and slope-compensation input pin. Connect this pin to the source lead of the flyback power MOSFET and the external current sensing resistor. An optional series resistor between the CS pin and source of the power MOSFET can be used to adjsut the amplitude of the controller’s internal slope compensation.
VDD 5 P Bias supply pin for the controller. Typically connect this pin the output of an auxiliary bias winding from the flyback transformer, and to a resistor network from the line voltage to provide bias at start-up. Other bias schemes that do not violate the pin ratings of the device are permissible.
DRV 6 O Low-side gate-driver output optimized to drive low-cost silicon MOSFETs with up to 300 mA peak pull-up and 500 mA peak pull-down capability. A series gate resistor can be used to slow the turn-on and turn-off of the MOSFET to control high-frequency EMI.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.