JAJSOG3 December   2023 UCC28750

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Descriptions
      1. 7.3.1 VDD - Input Bias
      2. 7.3.2 DRV - Gate Drive Out
      3. 7.3.3 CS - Current Sensing
      4. 7.3.4 FB - Feedback
      5. 7.3.5 FLT - Fault
      6. 7.3.6 GND - Ground Return
    4. 7.4 Feature Description
      1. 7.4.1 Soft Start
      2. 7.4.2 Control Law
      3. 7.4.3 Frequency Dithering
      4. 7.4.4 Fault Protections
        1. 7.4.4.1 VDD Overvoltage and Undervoltage Lockout
        2. 7.4.4.2 Internal Overtemperature Protection
        3. 7.4.4.3 Output Overpower Protection
        4. 7.4.4.4 Output Short-Circuit Protection
        5. 7.4.4.5 FLT Pin Protections
      5. 7.4.5 Slope Compensation
    5. 7.5 Device Functional Modes
      1. 7.5.1 Off
      2. 7.5.2 Startup
      3. 7.5.3 On
      4. 7.5.4 Fault
      5. 7.5.5 Disabled
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Bulk Capacitance with Minimum Bulk Voltage
        2. 8.2.3.2 Transformer Turns Ratio and Inductance
        3. 8.2.3.3 Current Sense and Slope Compensation Network
        4. 8.2.3.4 Output Capacitors
        5. 8.2.3.5 VDD Capacitance, CVDD
      4. 8.2.4 Application Performance Plots
        1. 8.2.4.1 Startup
        2. 8.2.4.2 Load Transients
        3. 8.2.4.3 Q1 Drain Voltage Evaluation
      5. 8.2.5 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Output Capacitors

The output capacitor value is determined by two factors in a power supply design: steady state ripple voltage and the output transient voltage response. The capacitor values for the transient response are typically specified as a load step from no load to full load of the power supply design.

Equation 23. C out = I step × t response Δ V out

Where

  • Istep is the largest step in load current
  • tresponse is the approximate response time
  • ΔVout is the allowable output voltage change

Equation 24. t response = 0.33 f c + T sw

Where

  • fc is the approximate crossover frequency, typically set to one-tenth the switching frequency
  • Tsw is the switching period expected at the initial load condition before the load step

The ripple voltage in steady state has two major contributors: the change in the output voltage due to the charge and discharge of the output capacitors in every switching cycle, and the step in the output voltage due to the equivalent series resistor of the capacitors. An additional margin is placed on the ESR calculation to account for variance and aging of the

Equation 25. ESR V ripple i pk,max × N PS × 50 %
Equation 26. C ripple = I out,max × D max V ripple × f sw

Where

  • Vripple is the allowable voltage ripple for a design
  • NPS is the primary to secondary turns ratio
  • Iout,max is the maximum output load current
  • ipk, max is the primary side maximum peak current of the transformer

The final output capacitor value is the larger of the Cout and Cripple values. The estimated crossover frequency largely determines the value of capacitance to use. For example, a crossover frequency of 2.5kHz suggests to use 900μF, while a 6.5kHz crossover is much lower capacitance, about 350μF. Use multiple capacitors to lower the equivalent ESR and get the actual capacitance close to the nameplate capacitance. Multiple capacitors increase robustness by accounting for DC derating and temperature rating fluctuations in the capacitance value.