JAJSOG3 December   2023 UCC28750

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Descriptions
      1. 7.3.1 VDD - Input Bias
      2. 7.3.2 DRV - Gate Drive Out
      3. 7.3.3 CS - Current Sensing
      4. 7.3.4 FB - Feedback
      5. 7.3.5 FLT - Fault
      6. 7.3.6 GND - Ground Return
    4. 7.4 Feature Description
      1. 7.4.1 Soft Start
      2. 7.4.2 Control Law
      3. 7.4.3 Frequency Dithering
      4. 7.4.4 Fault Protections
        1. 7.4.4.1 VDD Overvoltage and Undervoltage Lockout
        2. 7.4.4.2 Internal Overtemperature Protection
        3. 7.4.4.3 Output Overpower Protection
        4. 7.4.4.4 Output Short-Circuit Protection
        5. 7.4.4.5 FLT Pin Protections
      5. 7.4.5 Slope Compensation
    5. 7.5 Device Functional Modes
      1. 7.5.1 Off
      2. 7.5.2 Startup
      3. 7.5.3 On
      4. 7.5.4 Fault
      5. 7.5.5 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Bulk Capacitance with Minimum Bulk Voltage
        2. 8.2.3.2 Transformer Turns Ratio and Inductance
        3. 8.2.3.3 Current Sense and Slope Compensation Network
        4. 8.2.3.4 Output Capacitors
        5. 8.2.3.5 VDD Capacitance, CVDD
      4. 8.2.4 Application Performance Plots
        1. 8.2.4.1 Startup
        2. 8.2.4.2 Load Transients
        3. 8.2.4.3 Q1 Drain Voltage Evaluation
      5. 8.2.5 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Unless otherwise specified, VDD = 20 V; VFB = 2.3 V; VFLT = 2 V; TA = 25 ℃; CDRV = 1000 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD PIN
Vuvlo(on) VDD undervoltage-lockout turn-on voltage (rising) -40℃ < TJ < 125℃ 14.3 15.3 16.3 V
Vuvlo(off) VDD undervoltage-lockout turn-off voltage (falling) -40℃ < TJ < 125℃ 8 9 10 V
Vovlo(1) VDD overvoltage-lockout threshold VFB = 2.3 V 26 28 30 V
Vpor(1) Power-on reset level (latch-off fault un-latches, IC reset) 5 V
IVDD(start) Start-up controller bias current VVDD = 14 V 5 10 μA
IVDD(on) Operating controller bias current UCC287501/2/3/4 (65 kHz) fSW = 65 kHz
CDRV = 1000 pF
VFB = 2.3 V		 1.8 2.5 mA
UCC287505/6/7/8 (100 kHz) fSW = 100 kHz
CDRV = 1000 pF
VFB = 2.3 V		 2 2.7 mA
IVDD(wait)(1) Wait state bias current FB Pin bias current subracted from value 360 μA
IVDD(fault)(1) Fault state controller bias current FB Pin bias current subracted from value 360 μA
IVDD(dis)(1) Disabled state controller bias current VFLT = 0 V 250 μA
FB PIN (1)
RFB Pull-up resistor 10 kΩ
VFB(offset) Internal offset of VFB 0.8 V
GFB FB pin to CS pin ratio 2 V/V
IFB(short) FB pin short circuit current 0.5 mA
V0peak Feedback voltage pin threshold to clamp maximum switching frequency 3.0 V
V1norm Feedback voltage threshold to operate at the fixed switching frequency 2.6 V
V2foldback Feedback voltage pin threshold to linearly lower switching frequency 2.0 V
V3burst Feedback voltage pin threshold to enter burst mode 1.2 V
V4stop Feedback voltage pin threshold to stop switching 1.1 V
Vopen Feedback voltage open loop 5 V
Vopp Feedback voltage which starts the over-power protection fault timer Duty cycle > 60-% 2.6 V
DRV PIN (1)
Isource(pk)(1) Peak driver source current 300 mA
Isink(pk)(1) Peak driver sink current 500 mA
ROL(1) Pull-down resistance (off-state) VDD = VUVLO(off) + 100 mV, IDRV = 1 mA 5 Ω
VDRV(clamp)(1) DRV voltage clamp VDD = 20 V 12 V
VDD = Vuvlo(off) + 100 mV 8 V
FLT PIN
Vbrownout (1) Voltage on FLT pin which causes the controller to stop switching when a brownout event is detected  1.4 V
Ibrownout(1) Current source which changes the threshold of Vbrownout after a brown-in event, providing hysteresis 4 μA
FLThyst(brownout)(1) Hysteresis on FLT pin for the brownout threshold. The FLT pin must cross Vbrownout + FLThyst(brownout) to enable switching operation 50 mV
VFLT(open)(1) Voltage on FLT pin when nothing is connected UCC287502/4/6/8 2.3 V
VFLT(ovp) Voltage on FLT pin which causes the controller to stop switching when an overvoltage event occurs 3.8 4.1 4.3 V
FLThyst(ovp)(1) Hyteresis on FLT pin for the overvoltage protection threshold 100 mV
IFLT(ovp, clamp)(1) Current sink that is enabled during the OVP fault  500 μA
IFLT(tsd)(1) Current source out of the pin into an NTC resistor for external over-temperature fault 100 μA
VFLT(tsd)(1) Voltage on FLT pin which causes the controller to stop switching when an overtemperature even occurs 0.95 1 1.05 V
FLThyst(tsd)(1) Hysteresis on FLT pin for the thermal shutdown theshold  200 mV
VFLT(dis) Voltage on FLT pin which causes the controller to stop switching when the pin is pulled below the threshold 0.45 0.5 0.55 V
FLThyst(dis)(1) Hysteresis on FLT pin for the disable theshold  100 mV
tprop(dis)(1) Propagation from the time when the disable fault occurs to the time when the controller stops switching 1 µs
CS PIN AND INTERNAL SLOPE-COMPENSATION (1)
VCS(limit) CS peak current limit voltage VFB > V0Norm 900 mV
VCS(min) CS peak current limit voltage VFB < V3Burst 200 mV
tontime(min) Minimum on time possible, this is a sum of the tprop(ocl) and tleb specifications 310 ns
tprop(ocl) Current limit propagation delay 60 ns
tleb Leading edge blanking time 250 ns
tss Soft-start time 4.3 ms
Iramp(slope) Slope compensation current ramp amplitude VFB = 2.3 V 100 μA
INTERNAL THERMAL SHUTDOWN (1)
Tshut Internal die temperature that will stop device operation 160 ℃
Tshut(hyst) Thermal shutdown hysteresis 20 ℃
Tshut(rec) Internal die temperature to recover from thermal shutdown 140 ℃
(1) Specified by design, not production tested.