The P13 pin provides a regulated voltage to the gate of the depletion-mode MOSFET (Q_S), enabling Q_S to serve both V_VDD start-up and loss-less ZVS-sensing from the high-voltage switch node (V_SW) through the SWS pin. During V_VDD start-up, the UVLO circuit controls two power-path switches connecting SWS and P13 pins to VDD pin with two internal current-limit resistors (R_DDS and R_DDH), as shown in #X4050. In this configuration, Q_S behaves as a current source to charge the VDD capacitor (C_VDD). R_DDS is set at 5 kΩ when V_VDD < 1.8 V to limit the maximum fault current under a VDD short-to-GND condition. R_DDS is reduced to 500 Ω when V_VDD > 1.8 V to allow V_VDD to charge faster. The maximum charge current (I_SWS) is affected by R_DDS, the external series resistance (R_SWS) from SWS pin to Q_S, and the threshold voltage of Q_S (V_TH(Qs)). I_SWS can be calculated as

Figure 7-5 Operation of the VDD Startup Circuit

After V_VDD reaches V_VDD(ON), the two power-path switches open the connections between SWS, P13, and VDD pins. At this point, a third power-path switch connects an internal 13-V regulator to the P13 pin for configuring Q_S to perform loss-less ZVS sensing. Because the Q_S gate is fixed at 13 V, when the drain pin voltage of Q_S becomes higher than the sum of Q_S threshold voltage (V_TH(Qs)) and the 13-V gate voltage, Q_S turns off and the source pin voltage of Q_S can no longer follow the drain pin voltage change. This gate control method makes Q_S act as a high-voltage blocking device with the drain pin connected to V_SW. When the controller is switching, whenever V_SW is lower than 13 V, Q_S turns on and forces the source pin voltage to follow V_SW, becoming a replica of the V_SW waveform at the lower voltage level, as illustrated in #X4110.

The limited window for monitoring the V_SW waveform is sufficient for ZVS control of the UCC28781-Q1, since the ZVS tuning threshold (V_TH(SWS)) is set at 8.5 V for V_SET = 5 V and set at 4 V for V_SET = 0 V. The 8.5-V threshold is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial-ZVS condition using Si primary switches. On the other hand, performing full ZVS operation is more suitable with GaN primary switches. Using a 4-V threshold helps to compensate for sensing delay between V_SW and the SWS pin.

The internal 13-V regulator requires a high-quality ceramic by-pass capacitor (C_P13) between the P13 pin and AGND pin for noise filtering and providing compensation to the P13 regulator. The minimum C_P13 value is 1 μF and an X7R-type dielectric capacitor with 25-V rating or better is recommended. The controller enters a fault state if the P13 pin is open or shorted to AGND during V_VDD start-up, or if V_P13 overshoot is higher than V_P13(OV) of 15 V in run state. The output short-circuit current of P13 regulator (I_P13(MAX)) is self-limited to approximately 130 mA.

Since the P13 pin interfaces to the external depletion-FET, during input surge or EFT testing the Cgd of the depletion-FET can inject charge into the P13 pin and may cause an over-voltage stress. Under such condition it is recommended to place an 18-V Zener diode (D_P13) on the P13 pin to clamp its voltage below its abs-max level.

During AAM and ABM if the negative magnetizing current is large enough, a GaN device may operate in the reverse conduction condition before it turns on each switching cycle, so V_SW may be around -5 V for a brief inteval and it appears on the SWS pin. The SWS-pin design of UCC28781-Q1 can sustain –6 V (continuous) and –10 V (transient) stress to enhance the robust operation of the GaN power stage.

During this interval, Q_S is in the on-state and its body diode may conduct for a short time when the voltage drop across the on-state resistance of Q_S is high enough. The external R_SWS can limit the forward current flowing through the Q_S body diode, so the reverse recovery charge of the body diode can be significantly reduced. Too high of R_SWS value weakens the start-up charge current of C_VDD and results in a longer start-up time. R_SWS can be expected be slightly higher than 500 Ω. A small back-to-back TVS across BSS126 gate-to-source should be added to protect the gate-to-source voltage from potential abnormal voltage stress. Ensure that the TVS clamping voltage is less than the BSS126 gate-to-source voltage rating but does not conduct below 15 V.

R_SWS and a ceramic capacitor (C_SWS) between the SWS pin and the bulk input capacitor ground form a small sensing delay to help the internal detection circuit to identify the ZVS characteristic correctly. The delay is to ensure that the ZCD detection on the VS pin happens earlier than the ZVS detection on the SWS pin, such that the ZVS control can auto-tune the PWMH on-time in the proper direction. The minimum value of C_SWS is 22 pF.

Figure 7-6 ZVS Sensing by Reusing the VDD Startup Circuit