JAJSJ67E may 2020 – july 2023 UCC28782
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VDD INPUT | ||||||
| IRUN(STOP) | Supply current, run state | No switching | 0.88 | 2.2 | 2.66 | mA |
| IRUN(SW) | Supply current, run state | Switching, IVSL = 0 µA | 2.66 | 3 | 3.55 | mA |
| IWAIT | Supply current, wait state | IFB = -85 µA, VBIN = VBSW = VVDD = 20 V, sum of IBIN, IBSW, and IVDD | 452 | 580 | 695 | µA |
| IFB = -85 µA, BIN and BSW pins to AGND, IVDD only | 465 | 540 | 658 | µA | ||
| ISTART | Supply current, start state | VVDD = VVDD(ON) - 100 mV, VVS = 0 V | 150 | 235 | 301 | µA |
| IFAULT | Supply current, fault state | fault state | 500 | 630 | µA | |
| IVDD(LIMIT) | VDD startup current limit during startup | VVDD increasing, VSWS - VVDD = 1 V, VVDD = 16.5 V | 1.2 | 2 | 2.53 | mA |
| VVDD(ON) | VDD turnon threshold | VVDD increasing | 16.31 | 17 | 17.91 | V |
| VVDD(OFF) | VDD turnoff threshold | VVDD decreasing | 9.94 | 10.6 | 11.17 | V |
| VVDD(PCT) | Offset to power cycle for long output voltage overshoot | Offset above VVDD(OFF), IFB = -85 µA | 1.54 | 2.2 | 2.98 | V |
| VVDD(RST) | Logic reset threshold for latched fault | Voltage that VDD must cross H-L to reset a latched-off fault condition | 3.3 | 4.3 | 4.61 | V |
| VVDD(BOOST) | VDD regulation level in boost mode | IVDD = 0 mA to 30 mA, VBIN = 9 V | 17.6 | 18.5 | 19.4 | V |
| BIN INPUT | ||||||
| VBIN(ON) | UVLO on voltage of VBIN in boost mode | VBIN increasing | 2.03 | 2.2 | 2.42 | V |
| VBIN(OFF) | UVLO hysteresis below VBIN(ON) in boost mode | VBIN decreasing | 1.13 | 1.23 | 1.33 | V |
| VBIN(EN) | Highest VBIN to enable boost mode | VBIN decreasing | 14.44 | 14.9 | 15.47 | V |
| VBIN(DIS) | Hysteresis above VBIN(EN) to disable boost mode | VBIN increasing | 0.12 | 0.16 | 0.18 | V |
| BSW INPUT | ||||||
| RBSW | RDS(on) of internal boost switch | 0.94 | 1.4 | 2.28 | Ω | |
| IBSW(MAX) | Peak current threshold in CPC control | 0.27 | 0.335 | 0.38 | A | |
| tBLEB | Leading edge blanking time in boost mode | 129 | 190 | 247 | ns | |
| fBSW | Maximum switching frequency in CPC control, for UCC28782A only | VBIN = 9 V | 389 | 420 | 467 | kHz |
| fBSW | Maximum switching frequency in CPC control, for UCC28782AD, UCC28782BDL, and UCC28782CD only | VBIN = 9 V | 389 | 420 | 499 | kHz |
| tBOFF(MIN) | Minimum off time in COT control | IFB = -85 µA | 198 | 255 | 353 | ns |
| IBSW = 500 mA | 2.9 | 4.35 | 5.9 | μs | ||
| P13 OUTPUT | ||||||
| VP13 | P13 voltage level including load regulation | 0 mA to 60 mA out of P13, run state, VVDD = 20 V | 12.0 | 12.8 | 13.6 | V |
| IP13(START) | Max sink current of P13 pin during startup | VP13 = 14 V | 1.53 | 2.2 | 3.04 | mA |
| IP13(MAX) | Current sourcing limit of P13 pin | P13 shorted to AGND, VVDD = 20 V | 103.3 | 133 | 154.5 | mA |
| VR13(LINE) | Line regulation of VP13 | VVDD = 15 V to 35 V | -6 | 2 | 8.7 | mV |
| VP13(OV) | Over voltage fault threshold above VP13 | 1.35 | 2 | 2.54 | V | |
| RP13 | Dropout resistance of P13 regulator switch between VDD and P13 pins | (VVDD - VP13) / 30 mA, VVDD = 11 V, 30 mA out of P13 | 8.5 | 13 | 22.7 | Ω |
| S13 OUTPUT | ||||||
| RS13 | RDS(on) of internal disconnect switch between P13 and S13 pins | (VP13 - VS13) / 30 mA, VVDD = 11 V, 30 mA out of S13 | 2.1 | 2.8 | 3.82 | Ω |
| VS13_OK | S13_OK threshold to enable switching | VRUN = 5 V | 9.63 | 10.2 | 10.7 | V |
| IS13(MAX) | Current sourcing limit of S13 pin | S13 shorted to AGND, VVDD = 20 V | 260.7 | 350 | 452.5 | mA |
| REF OUTPUT | ||||||
| VREF | REF voltage level | IREF = 0 A | 4.9 | 5 | 5.13 | V |
| IREF(MAX) | Current sourcing limit of REF pin | REF shorted to AGND, VVDD = 20 V | 14.3 | 17 | 20.3 | mA |
| VR5(LINE) | Line regulation of VREF | VVDD = 12 V to 35 V | -7 | -3 | 1 | mV |
| VR5(LOAD) | Load regulation of VREF | 0 mA to 1 mA out of REF, change in VREF | -16 | 0.1 | 25 | mV |
| VS INPUT | ||||||
| VVSNC | Negative clamp level | IVSL = -1.25 mA, voltage below ground | 221 | 287 | 344 | mV |
| VZCD | Zero-crossing detection (ZCD) level | VVS decreasing | 12.4 | 35 | 67.2 | mV |
| IVSB | Input bias current | VVS = 4 V | -0.23 | 0 | 0.31 | µA |
| VVS(SM1) | VS threshold voltage in SM1 startup mode | 242.4 | 282 | 318.3 | mV | |
| VVS(SM2) | VS threshold voltage in SM2 startup mode | 458.3 | 500 | 543 | mV | |
| VVSLV(UP) | VS upper threshold out of low output voltage mode (LV mode) | VVS increasing | 2.41 | 2.49 | 2.6 | V |
| VVSLV(LR) | VS lower threshold into low output voltage mode (LV mode) | VVS decreasing | 2.3 | 2.39 | 2.49 | V |
| tZC | Zero-crossing timeout delay | 1.95 | 2.3 | 2.73 | µs | |
| tD(ZCD) | Propagation delay from ZCD high to PWML 10 % high | VVS step from 4 V to -0.1 V | 23 | 50 | 81 | ns |
| CS INPUT | ||||||
| VCST(MAX) | Peak-power threshold on CS pin out of LV mode | IVSL = 0 μA, VVS ≥ VVSLV(UP) | 767.4 | 801 | 836.4 | mV |
| IVSL = -333 μA, VVS ≥ VVSLV(UP) | 650 | 727 | 788.7 | mV | ||
| IVSL = -666 μA, VVS ≥ VVSLV(UP) | 570 | 600 | 651.8 | mV | ||
| IVSL = -1.25 mA, VVS ≥ VVSLV(UP) | 537.2 | 570 | 612 | mV | ||
| VCST(MAX)_LV | Peak-power threshold on CS pin in LV mode | IVSL = 0 mA, VVS ≤ VVSLV(LR) | 593.7 | 628 | 663.9 | mV |
| IVSL = -666 μA, VVS ≤ VVSLV(LR) | 546 | 570 | 609.5 | mV | ||
| IVSL = -1.25 mA, VVS ≤ VVSLV(LR) | 511.2 | 540 | 584.7 | mV | ||
| VCST(MIN) | Minimum CS threshold voltage | VCS increasing, IFB = -85 µA | 120.7 | 153 | 200.1 | mV |
| KLC | Line-compensation current ratio | IVSL = -1.25 mA, IVSL / current out of CS pin | 21.6 | 25 | 29 | A/A |
| VCST(EMI)(1) | EMI dithering magnitude on CS pin out of LV mode | (VBUR / KBUR-CST) < VCST < VCST(MAX), IVSL < -646 μA, VVS ≥ VVSLV(UP) | 78.4 | 96 | 113.6 | mV |
| VCST(EMI)_LV(1) | EMI dithering magnitude on CS pin in LV mode | (VBUR / KBUR-CST) < VCST < VCST(MAX), IVSL < -646 μA, VVS ≤ VVSLV(LR) | 29.3 | 36 | 42.7 | mV |
| VCST(SM1) | CS threshold voltage in SM1 startup mode | VVS < VVS(SM1) | 177.5 | 200 | 222.9 | mV |
| VCST(SM2) | CS threshold voltage in SM2 startup mode | VVS < VVS(SM2) | 470.4 | 500 | 531.4 | mV |
| tCSLEB | Leading-edge-blanking time | VSET = 5 V, VCS = 1 V | 171.2 | 190 | 216.1 | ns |
| VSET = 0 V, VCS = 1 V | 94.4 | 108 | 125 | ns | ||
| tD(CS) | Propagation delay of CS comparator high to PWML 90 % low | VCS step from 0 V to 1 V | 10 | 26 | 34.8 | ns |
| fDITHER(1) | EMI dithering frequency on CS pin | (VBUR / KBUR-CST) < VCST < VCST(OPP), IVSL < -646 μA | 20 | 23 | 27 | kHz |
| BUR INPUT and Low-power MODE | ||||||
| KBUR-CST | Ratio of VBUR to VCST | VBUR between 0.7 V and 2.4 V | 3.82 | 3.98 | 4.09 | V/V |
| IBUR(LPM) | Bias source current of VBUR offset in LPM | 2.09 | 2.65 | 3.16 | µA | |
| IBUR(AAM) | Bias sink current of VBUR offset in AAM | VCST > VBUR / KBUR-CST | 3.76 | 4.85 | 5.81 | µA |
| fBUR(UP1) | First upper threshold of burst frequency in ABM | 30.7 | 34.4 | 38.5 | kHz | |
| fBUR(UP2) | Second upper threshold of burst frequency in ABM | VVS = 2.2 V | 41.8 | 51.2 | 58.9 | kHz |
| fBUR(LR) | Lower threshold of burst frequency in ABM | 21.3 | 24.5 | 28.1 | kHz | |
| fLPM | Burst frequency in low-power mode | 23.3 | 25 | 26.9 | kHz | |
| IPC INPUT and SBP2 MODE | ||||||
| VCST_IPC(UP) | Highest programmable VCST range of SBP2 by IPC pin | VIPC = 5 V | 373.8 | 405 | 438.5 | mV |
| KIPC | Ratio of the programmable IPC voltage to VCST | VIPC between 1.8 V and 3.8 V | 59.3 | 64 | 68.4 | mV/V |
| VCST_IPC(LR) | Lowest programmable VCST range of SBP2 by IPC pin | VIPC = 1 V | 247.5 | 273 | 307.7 | mV |
| VCST_IPC(MIN) | Minimum VCST of SBP2 by grounding IPC pin | VIPC = 0 V | 128.1 | 154 | 191.5 | mV |
| IIPC(SBP2) | Bias source current of VIPC offset in SBP2 | IFB = -85 µA | 40.7 | 49 | 55.7 | µA |
| fSBP2(UP) | Upper threshold of burst frequency in SBP2 | 6 | 8.5 | 13.4 | kHz | |
| fSBP2(LR) | Lower threshold of burst frequency in SBP2 | VIPC = 2 V | 1 | 1.7 | 2 | kHz |
| RUN | ||||||
| VRUNH | RUN pin high-level | IRUN = -0.2 mA | 4.6 | 4.78 | 5 | V |
| VRUNL | RUN pin low-level, for UCC28782A only | IRUN = 1 mA | 0.23 | 0.25 | 0.3 | V |
| VRUNL | RUN pin low-level, for UCC28782AD, UCC28782BDL, and UCC28782CD only | IRUN = 1 mA | 0.1 | 0.25 | 0.3 | V |
| ISRC(RUN) | RUN peak source current | VRUN = 2.3 V | 33 | 44 | 52 | mA |
| VRUN = 3 V | 14 | 20 | 25 | mA | ||
| tR(RUN) | Turn-on rise time of RUN, from 0 V to 2.5 V | CRUN = 22 nF, VRUN from 0 V to 2.5 V | 0.4 | 0.79 | 1 | µs |
| tF(RUN) | Turn-off fall time of RUN, 90 % to 10 % | CRUN = 10 pF | 20 | 32 | ns | |
| PWML | ||||||
| VPWMLH | PWML pin high-level | IPWML = -1 mA | 12.1 | 12.85 | 13.6 | V |
| VPWMLL | PWML pin low-level | IPWML = 1 mA | 0.002 | 0.1 | V | |
| ISRC(PWML)(1) | PWML peak source current | VPWML = 0 V | 0.25 | 0.5 | 0.8 | A |
| ISNK(PWML)(1) | PWML peak sink current | VPWML = 13 V | 1.2 | 1.9 | 2.8 | A |
| RSRC(PWML) | PWML pull-up resistance | IPWML = -20 mA | 3.1 | 4.3 | 6.1 | Ω |
| RSNK(PWML) | PWML pull-down resistance | IPWML = 20 mA | 0.5 | 1.1 | 1.9 | Ω |
| tR(PWML) | Turn-on rise time of PWML, 10 % to 90 % | CPWML = 1.5 nF | 30 | 53 | ns | |
| tF(PWML) | Turn-off fall time of PWML, 90 % to 10 % | CPWML = 1.5 nF | 9 | 20 | ns | |
| tD(RUN-PWML) | Delay from RUN high to PWML high | VS13 > 11 V | 1.92 | 4.7 | 7.43 | µs |
| tON(MIN) | Minimum on-time of PWML in LPM, for UCC28782A only | VSET = 5 V, IFB = -85 µA, VCS = 1 V | 68 | 105 | 172.5 | ns |
| tON(MIN) | Minimum on-time of PWML in LPM, for UCC28782AD, UCC28782BDL, and UCC28782CD only | VSET = 5 V, IFB = -85 µA, VCS = 1 V | 68 | 105 | 175 | ns |
| PWMH | ||||||
| VPWMHH | PWMH pin high-level | IPWMH = -1 mA | 4.39 | 4.66 | 4.83 | V |
| VPWMHL | PWMH pin low-level, for UCC28782A only | IPWMH = 1 mA | 0.19 | 0.198 | 0.21 | V |
| VPWMHL | PWMH pin low-level, for UCC28782AD, UCC28782BDL, and UCC28782CD only | IPWMH = 1 mA | 0.1 | 0.198 | 0.21 | V |
| ISRC(PWMH) | PWMH peak source current | VPWMH = 2.5 V | 16.5 | 21 | 26.2 | mA |
| VPWMH = 3.5 V | 3.8 | 6 | 7.6 | mA | ||
| tR(PWMH) | Turn-on rise time of PWMH, 10 % to 90 %, for UCC28782A only | CPWMH = 10 pF | 8 | 20 | ns | |
| tR(PWMH) | Turn-on rise time of PWMH, 10 % to 90 %, for UCC28782AD, UCC28782BDL, and UCC28782CD only | CPWMH = 10 pF | 8 | 24 | ns | |
| tF(PWMH) | Turn-off fall time of PWMH, 90 % to 10 % | CPWMH = 10 pF | 22 | 29 | ns | |
| tD(VS-PWMH) | Dead time between VS high and PWMH 10 % high | 10 | 18 | 28 | ns | |
| PROTECTION | ||||||
| VOVP | Over-voltage threshold | VVS increasing | 4.4 | 4.55 | 4.67 | V |
| VOCP | Over-current threshold | VCS increasing | 1.14 | 1.22 | 1.27 | V |
| KOPP-PPL | Ratio of over-power threshold to peak-power threshold | VCST(OPP) / VCST(MAX) , and VCST(OPP)_LV / VCST(MAX)_LV | 0.72 | 0.75 | 0.78 | V/V |
| IVSL(RUN) | VS line-sense run current | Current out of VS pin increasing | 313 | 365 | 408.6 | µA |
| IVSL(STOP) | VS line-sense stop current | Current out of VS pin decreasing | 255 | 305 | 336.4 | µA |
| KVSL | VS line sense ratio | IVSL(STOP) / IVSL(RUN) | 0.72 | 0.836 | 0.9 | A/A |
| RRDM(TH) | RRDM threshold for CS pin fault | 35 | 55 | 70 | kΩ | |
| TJ(STOP) | Thermal-shutdown temperature | Internal junction temperature | 125 | 162 | °C | |
| VBOVPTH | Shut-down voltage of VVDD for boost output OVP | 21.5 | 25 | 28.2 | V | |
| VBOVPR | Recovery voltage of VVDD for boost output OVP | 16.8 | 20 | 23.3 | V | |
| tOPP | OPP fault timer, for UCC28782A only | IFB = 0 A | 133.3 | 164 | 201.1 | ms |
| tOPP | OPP fault timer, for UCC28782AD, UCC28782BDL, and UCC28782CD only | IFB = 0 A | 130 | 164 | 201.1 | ms |
| tBO | Brown-out detection delay time | IVSL < IVSL(STOP) | 28.8 | 55 | 85.2 | ms |
| tCSF1 | Maximum PWML on-time for detecting CS pin fault | VSET = 5 V | 1.6 | 2.05 | 2.5 | µs |
| tCSF0 | Maximum PWML on-time for detecting CS pin fault | RRDM < RRDM(TH) for VSET = 0 V | 0.85 | 1.05 | 1.27 | µs |
| tFDR | Fault reset delay timer, for UCC28782A only | OCP, OPP, OVP, SCP or CS pin fault | 1.2 | 1.5 | 2.22 | s |
| tFDR | Fault reset delay timer, for UCC28782AD, UCC28782BDL, and UCC28782CD only | OCP, OPP, OVP, SCP or CS pin fault | 1.2 | 1.5 | 2.25 | s |
| FLT INPUT | ||||||
| VNTCTH | NTC shut-down voltage | FLT voltage decreasing | 0.47 | 0.5 | 0.52 | V |
| RNTCTH | NTC shut-down resistance | RNTC decreasing | 8.9 | 9.91 | 11.18 | kΩ |
| RNTCR | NTC recovery resistance | RNTC increasing | 21.2 | 23 | 26.4 | kΩ |
| IFLT | Input bias current for VFLT at VIOVPTH | VFLT = 4.5 V | -0.1 | 0 | 0.1 | µA |
| VIOVPTH | Shut-down voltage of input OVP | FLT voltage increasing | 4.3 | 4.5 | 4.67 | V |
| VIOVPR | Hysteresis of input OVP | FLT voltage increasing | 57.7 | 74 | 87 | mV |
| tFLT(NTC) | Delay time of NTC fault | 14 | 50 | 100 | µs | |
| tFLT(IOVP) | Delay time of input OVP fault | 555 | 750 | 917 | µs | |
| VFLTZ | Clamp voltage of FLT pin | IFLT = 150 µA | 5.08 | 5.5 | 5.61 | V |
| RTZ INPUT | ||||||
| KTZ | tZ compensation ratio | Ratio of tZ at IVSL = -200 µA to tZ at IVSL = -733 µA | 1.27 | 1.41 | 1.54 | s/s |
| tZ(MAX) | Maximum programmable dead time from PWMH low to PWML high | RRTZ = 280 kΩ, IVSL = -1 mA, VSET = 5 V | 397.8 | 478 | 592.8 | ns |
| tZ(MIN) | Minimum programmable dead time from PWMH low to PWML high | RRTZ = 78.4 kΩ, IVSL = -1 mA, VSET = 0 V | 56.1 | 70 | 89.1 | ns |
| tZ | Dead time from PWMH low to PWML high | IVSL = -200 µA | 152.2 | 175 | 212.7 | ns |
| IVSL = -450 µA | 129.2 | 150 | 190 | ns | ||
| IVSL = -733 µA | 109.7 | 125 | 147.2 | ns | ||
| SWS INPUT | ||||||
| VTH(SWS) | SWS zero voltage threshold | VSET = 5 V | 8.1 | 8.5 | 9.1 | V |
| VSET = 0 V | 3.7 | 4.04 | 4.4 | V | ||
| tD(SWS-PWML) | Time between SWS low to PWML 10 % high | VSWS step from 5 V to 0 V | 11.4 | 17 | 24.8 | ns |
| FB INPUT | ||||||
| IFB(SBP) | Maximum control FB current | IFB increasing | 64.2 | 75 | 87.1 | µA |
| VFB(REG) | Regulated FB voltage level | 4.02 | 4.25 | 4.53 | V | |
| RFBI | FB input resistance | 7.5 | 8.3 | 9.6 | kΩ | |
| dICOMP/dt(1) | Slope of internal ramp compensation current | 0.192 | 0.214 | 0.236 | A/s | |
| ICOMP | Magnitude of internal ramp compensation current | 4 | 6.75 | 8 | µA | |
| RDM INPUT | ||||||
| tDM(MAX) | Maximum PWMH width with maximum tuning, for UCC28782A only | VSWS = 12 V | 6.32 | 6.95 | 7.53 | µs |
| tDM(MAX) | Maximum PWMH width with maximum tuning, for UCC28782AD, UCC28782BDL, and UCC28782CD only | VSWS = 12 V | 6.0 | 6.95 | 7.53 | µs |
| tDM(MIN) | Minimum PWMH width with minimum tuning, for UCC28782A only | VSWS = 0 V | 3.11 | 3.43 | 3.77 | µs |
| tDM(MIN) | Minimum PWMH width with minimum tuning, for UCC28782AD, UCC28782BDL, and UCC28782CD only | VSWS = 0 V | 3.0 | 3.43 | 3.77 | µs |
| XCD INPUT (for UCC28782AD, UCC28782BDL, and UCC28782CD only) | ||||||
| VXCD(LR) | XCD lower zero-crossing threshold | 5.9 | 6.62 | 7.2 | V | |
| VXCD(UP) | XCD upper zero-crossing threshold | 6.8 | 7.5 | 7.9 | V | |
| IXCD(0) | Leakage current in XCD wait state | VXCD = 15 V | 0.3 | 1.7 | µA | |
| IXCD(1) | First-step XCD sense current | VXCD = 15 V | 0.32 | 0.4 | 0.46 | mA |
| IXCD(2) | Second-step XCD sense current | VXCD = 15 V | 0.61 | 0.775 | 0.91 | mA |
| IXCD(3) | Third-step XCD sense current | VXCD = 15 V | 0.73 | 1.15 | 1.6 | mA |
| IXCD(4) | Fourth-step XCD sense current | VXCD = 15 V | 1.2 | 1.53 | 1.81 | mA |
| IXCD(MAX) | Maximum XCD discharge current | VXCD = 15 V | 1.65 | 2 | 2.5 | mA |
| VXCD(OVP) | Clamping voltage for XCD OVP | IXCD = 20 mA | 23 | 26 | 30 | V |
| tXCD(STEP) | Dwell time for each XCD sense step, for UCC28782A only | 10 | 12 | 14 | ms | |
| tXCD(STEP) | Dwell time for each XCD sense step, for UCC28782AD, UCC28782BDL, and UCC28782CD only | 9 | 12 | 14 | ms | |
| tXCD(MAX) | Maximum XCD discharge time | 230.4 | 300 | 373.3 | ms | |
| tXCD(WAIT) | XCD wait time | 700 | 1071 | ms | ||