The dead-time optimizer in Figure 8-18 controls the two dead-times: the dead-time between PWMH falling edge and PWML rising edge (t_Z), as well as the dead-time between PWML falling edge and PWMH rising edge (t_D(PWML-H)).

Similar to UCC28780, the adaptive control law for t_Z of UCC28782 utilizes the line feed-forward signal to extend t_Z as V_BULK reduces, as shown in Figure 8-20. The VS pin senses V_BULK through the auxiliary winding voltage (V_AUX) when the low-side switch (Q_L) is on. The auxiliary winding creates a line-sensing current (I_VSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (R_VS1). Minimum t_Z (t_Z(MIN)) is set at V_BULK(MAX) through the RTZ pin. When I_VSL is lower than 666 μA, t_Z linearly increases and the maximum t_Z extension is 140% of t_Z(MIN).

Figure 8-20 t_Z Control Optimized for Wide Input Voltage Range

Figure 8-21 The Enhanced t_Z Control for CCM Avoidance

The enhanced t_Z control of UCC28782 helps to avoid voltage stress on the secondary rectifier due to temporary continuous conduction mode (CCM) operation. If the high side switch turns off under a higher than normal negative resonant current instance, the switch node voltage (V_SW) and the auxiliary winding voltage (V_AUX) will drop very fast, because a higher di/dt current flows through the leakage inductance. At the same instant, if the magnetizing current has not decayed down to zero yet, the current will continue to flow in the secondary rectifier, so the switch node voltage will recover back to a high level again and results in a short-duration voltage dip behavior within the t_Z period. If a ACF controller turns on the low-side switch after t_Z expires but the magnetizing current is still positive, the limited turn off speed of the synchronous rectifier (SR) will result in a higher di/dt current as the low-side switch turns on, so a high voltage spike is generated on the SR drain-to-source voltage. Then, the FET voltage rating or the snubber design on the secondary side may need to be compromised, which are the typical concerns of flyback topology in CCM. Therefore, the VS pin of UCC28782 can detect this event and avoid low-side switch turn on after t_Z expires under this situation.

The concept is to detect the ZCD signal once again at the instant of t_Z expiration, such that the controller will not respond to the false ZCD signal after the high side switch turns off. When the duration of the voltage dip is shorter than t_Z setting, the ZCD signal will change back to its original low state at the t_Z expiration instance. When there is no valid switch node voltage transition detected from the ZCD signal at the instance, the controller will wait for another ZCD rising edge to trigger the low-side switch turn-on of the next cycle. Since the next ZCD signal could be a real indication of the magnetizing current reached to 0 A, the CCM turn-off event of secondary rectifier will not occur. Figure 8-21 illustrates the issue and the operation principle of the improved switching control in UCC28782.

The control law for t_D(PWML-H) of UCC28782 is adaptive with the slope variation of the switching node voltage, regardless of the SET-pin voltage. One reason of applying the adaptive control is to generate a minimum dead time for reducing the body diode conduction time of the high-side Si switch or the reverse conduction time of the high-side GaN switch. Another reason is to avoid the risk of hard switching. Since the rising slope of the switch node voltage varies with different peak magnetizing currents as output load changes, using a fixed dead-time can potentially cause hard-switching on the high-side clamp switch (Q_H) if the dead-time is not long enough.

Figure 8-22 t_D(PWML-H) Control Optimized for GaN and Si FETs

For the GaN ACF with UCC28780, a fixed 40-ns dead time from PWML falling edge to PWMH rising edge is applied for the SET pin connected to GND. For the Si ACF with UCC28780, the adaptive dead time adjustment based on the ZCD falling edge plus 40-ns delay is applied for the SET pin connected to the REF pin. The enhanced t_D(PWML-H) control of UCC28782 helps to further reduce the body diode conduction time of the high side Si switch or the reverse conduction time of the high-side GaN switch without risk of hard switching on the high side switch. Moreover, the same dead time control is generalized for both SET-pin connections. After the ZCD falling edge is detected, the PWMH driver of UCC28782 will pull high immediately, and the extra 40-ns delay in UCC28780 is removed. For the GaN ACF with UCC28782, as long as the VS-pin delay from the parasitic capacitive loading is reduced by a proper layout arrangement, it is possible to shorten the reverse conduction time in heavy load, and also eliminate the concern of high-side hard switching in light load. For the Si ACF with UCC28782, the propagation delay of the high-side driver already provides enough margin for switch node voltage settled to a high level after ZCD falling edge is triggered, so there is no need to introduce an extra 40-ns delay like UCC28780.