JAJSJ67E may 2020 – july 2023 UCC28782
PRODUCTION DATA
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NUMBER | ||
| FLT | 1 | I | The controller enters into the fault state if the FLT-pin voltage is pulled above 4.5 V or below 0.5 V. A 50-µA current source interfaces directly with an external NTC (negative temperature coefficient) thermistor to AGND pin for remote temperature sensing. The current source is active during the run state and inactive during the wait state. A 50-µs fault delay allows a filter capacitor to be placed on the FLT pin without false triggering the 0.5-V OTP fault when the controller enters into a run state from a wait state. Alternatively, a high-resistance voltage divider can be used to sense the bulk input capacitor voltage for line-OVP detection, and a 750-µs fault delay helps to prevent false triggering the 4.5-V input line-OVP from a short-duration bulk capacitor voltage overshoot during line surge and ESD strike events. When FLT-pin voltage is used for line-OVP detection, the external OTP can be implemented on CS pin. |
| RTZ | 2 | I | A resistor between this pin and AGND pin programs an adaptive delay for transition to zero voltage from the turn-off edge of the high-side clamp switch to the turn-on edge of the low-side switch. The parasitic capacitance between this pin and AGND needs to be minimized to avoid its effect on the dead-time calculation. |
| RDM | 3 | I | A resistor between this pin and AGND pin programs a synthesized demagnetization time used to control the on-time of the high-side switch to achieve zero voltage switching on the low-side switch. The controller applies a voltage on this pin that varies with the output voltage derived from the VS pin signal. The parasitic capacitance between this pin and AGND needs to be minimized to reduce its influence on the internal PWMH on-time calculation. |
| IPC | 4 | I | This pin is an intelligent power control (IPC) pin to optimize the converter efficiency. A 50-µA current source directly interfaces with a resistor (RIPC) to AGND pin to program an increase in the peak current level at very light load; the burst frequency can be further reduced, helping to achieve low standby power and tiny-load power. If the IPC pin is connected to AGND without RIPC, the peak current level in very light load is set to a minimum level for the output ripple or audible noise sensitive designs. RIPC can also be connected between this pin and the CS pin or IPC pin can be directly connected to CS pin, so the 50-µA IPC current can create an output voltage dependent offset voltage on the CS pin for reducing output ripple in adaptive burst mode and improving light-load efficiency at lower output voltage level of a wide output voltage range design. IPC pin can be used to disable the PFC controller at all load condition of 5 V and 9 V outputs through a control switch to further improve the light load efficiency of higher power adapters. |
| BUR | 5 | I | This pin is used to program the burst threshold of the converter at light load. A resistor divider between REF pin and AGND pin is used to set a voltage at this pin to determine the peak current level when the converter enters adaptive burst mode (ABM). In addition, the Thevenin resistance on BUR pin (equivalent resistance of the divider resistors in parallel) is used to set an offset voltage for smooth mode transition. A 2.7-µA pull up current increases the peak current threshold when the converter enters low power mode (LPM) from ABM. A 5-µA pull down current reduces the peak current threshold when the converter enters into heavy load mode (adaptive amplitude modulation, AAM) from ABM. |
| FB | 6 | I | The feedback current signal to close the converter regulation loop is coupled to this pin. This pin presents a 4.25-V output that is designed to have 0-µA to 75-µA current pulled out of the pin corresponding to the converter operating from full-power to zero-power conditions. A 220-pF filter capacitor between FB pin and REF pin is recommended to desensitize the feedback signal from noise interference. |
| REF | 7 | O | The pin is a 5-V reference output that requires a 0.22-µF ceramic bypass capacitor to the AGND pin. This reference is used to power internal circuits and can supply a limited external load current. Pulling this pin low shuts down PWM action and initiates a VDD restart. |
| AGND | 8 | G | Analog ground and the ground return of PWMH and RUN drivers. Return all analog control signals to this ground. |
| CS | 9 | I | This is the current-sense input pin. This pin couples to the current-sense resistor through a line-compensation resistor to control the peak primary current in each switching cycle. An internal current source on this pin, proportional to the converter’s input voltage, creates an offset voltage across the line-compensation resistor to balance the OPP level across line. The CS pin can also provide an alternative OTP function, when the FLT pin is being used for the line input-OVP. A small-signal diode in series with an NTC resistor is connected between PWMH pin and CS pin to form the OTP detection. When PWMH is high, the NTC resistor and the line-compensation resistor become a resistor divider from 5 V and creates a temperature dependent voltage on CS pin. When CS pin voltage is higher than 1.2 V in PWMH on state for 2 consecutive cycles, the OTP fault on CS pin is triggered. |
| RUN | 10 | O | This output pin is high when the controller is in a run state. This output is low during start-up, wait, and fault states. A 2.2-µs timer delays the initiation of PWML switching after this pin has gone high and S13-pin voltage is above the 10-V power good threshold. The pull up driving capability of both RUN and PWMH pins allows bias power management of a digital isolator and GaN power IC through a common-cathode small-signal diode, so the power consumption can be reduced in wait state. |
| PGND | 11 | G | Low-side ground return of the PWML driver. The internal level shifter allows the common return impedance to be eliminated, and improving higher frequency operation. For a GaN-based gate-injection transistor (GIT), this pin can be directly connected to the separate source pin of a GIT GaN device, which enhances the turn-off speed and decouples the additional voltage spike on the current-sense resistor and layout parasitic inductance of the gate driving loop. For a silicon (Si) power FET, this pin can be connected to the source for a smaller gate driving loop. For a GaN power IC with a logic PWM input, this pin can be referred to AGND. |
| PWML | 12 | O | Low-side switch gate driver output. The high-current capability (-0.5A/+1.9A) of PWML enables driving of a silicon power MOSFET with higher capacitive loading, a GIT GaN with continuous on-state current, or a GaN power IC with logic input. The maximum voltage level of PWML is clamped to the P13 pin voltage. |
| S13 | 13 | O | S13 is coupled to P13 through an internal 2.8-Ω switch controlled by the RUN pin. When RUN is high, the S13 decoupling capacitor is charged up to 13 V by an internal soft-start current limiter. The S13 pin voltage needs to increase above 10 V to initiate PWML switching. When RUN is low, S13 is discharged by the S13 pin loading, such as GaN power IC. The power-on delay of the GaN power IC on S13 must be less than 2 µs to be responsive to PWML. A 22-nF ceramic capacitor between S13 and the driver ground is recommended. S13 can also perform power management on the PFC controller at the same time through a diode, such that PFC can be disabled at deep light load condition. |
| P13 | 14 | O | P13 is a regulated 13-V output voltage derived from VVDD. During VVDD startup, P13 pin is connected to the VDD pin internally, so the external high-voltage depletion MOSFET, such as BSS126, can provide the controlled startup current to charge the VDD capacitor. After the initial startup, P13 recovers back to 13-V regulation. A 1-µF ceramic bypass capacitor is required from P13 to AGND. A 20-V Zener between this pin and AGND is recommended to protect this pin from overstress, when the connection between this pin and the BSS126 gate is fail-open or line surge energy is coupled to this pin. |
| PWMH | 15 | O | PWM output signal used to control the gate of the high-side clamp switch through an external high-voltage gate driver. The driving capability is designed to bias an external level-shifting isolator through a small-signal diode or can also transmit the signal to high-side driving circuitry through a pulse transformer. The maximum voltage level of PWMH is clamped to 5-V REF level. |
| SWS | 16 | I | This sensing input is used to monitor the switch-node voltage as it nears zero volts in normal operation for ZVS auto-tuning. The source of a high-voltage depletion-mode MOSFET, such as BSS126, is coupled to this pin through a current-limiting resistor, so only the useful switching characteristic below 15 V is monitored. During start-up, this pin is connected to the VDD pin internally to allow BSS126 to provide start-up current. The external current-limit resistor and a small bidirectional TVS across BSS126 gate and source should be added to protect the gate-to-source voltage from potential abnormal voltage stress. The resistor should be higher than 500 Ω. The clamping voltage of TVS should be less than BSS126 voltage rating but greater than 15 V. Moreover, the resistor and a 22-pF ceramic capacitor between the SWS pin and the bulk input capacitor ground form a small sensing delay to help the internal detection circuit to identify the ZVS characteristic correctly. |
| XCD | 17, 18 | I | X-cap discharge input pins with 2-mA maximum discharge current capability. The 6.5-V line zero-crossing (LZC) threshold on XCD pins is used to detect AC-line presence. When LZC is missing over an 84-ms timeout period, the discharge current is enabled for a maximum period of 300 ms followed by a 700-ms no current blanking time. For the latched-off fault protections, when AC-line recovers and LZC is detected again, the controller can reset the latch fault state almost immediately and will attempt to restart without waiting to fully discharge the bulk input capacitor. For the auto-recovery fault protections, if the controller is in 1.5-s auto-recovery fault state, LZC can reset the timer and speed up the restart attempt. The two redundant XCD pins help to provide the X-cap discharge function even when one pin is in fail-open condition. To form the discharge path, an anode of two high-voltage diode rectifiers is connected to each X-cap terminal, the two diode cathodes are connected together to a 26-kΩ high-voltage current-limiting resistance, and the drain-to-source connection of a high-voltage depletion MOSFET couples the resistance to the XCD pins. Two series 13-kΩ SMD resistors in 1206 size can be used as the current limiting device, and share the potential transient voltage from the AC-line. A 600-V rated MOSFET such as BSS126 is needed as the high voltage blocking device. The MOSFET gate is connected to the P13 pin, so the XCD pins can obtain enough signal headroom for LZC detection. If the X-cap discharge function is not needed, XCD pins must be connected to AGND pin to disable the function, and the diode-resistor-MOSFET path must be removed. Different from UCC28782AD, UCC28782BDL, and UCC28782CD, the same pin locations on UCC28782A are defined as two additional AGND pins, keeping the XCD-pin function disabled. |
| VDD | 19 | P | Controller bias power input. VDD pin is also the integrated boost converter output pin. A hold-up capacitor to BGND pin is required. For fixed-output applications where the boost converter is optional, VDD pin can directly connect to the rectified primary-side auxiliary winding voltage, so the boost-converter components can be eliminated. For wide-output design with the boost converter, a ceramic capacitor with 10-µF or 15-µF capacitance is recommended, and the minimum voltage rating is 25 V. |
| BGND | 20 | G | Boost converter return pin connected to the source terminal of the internal 30-V boost switch. The separate ground return simplifies PCB layout design to minimize the high di/dt switching loop along with the boost diode and VDD capacitor, so the noise-coupling effect to other sensitive nodes can be mitigated. |
| BSW | 21 | I | Boost converter switch node, connected to the drain terminal of internal 30-V boost switch. For wide output voltage applications, the boost inductor and boost diode anode are connected to this pin. For a fixed output voltage design, BIN and BSW pins should be connected to BGND pin, so the boost-converter control is disabled in order to lower the controller run current. A 22-µH inductor with higher than 0.4-A saturation current capability and less than 1 Ω resistance is recommended for boost inductor selection. If the maximum VDD-pin voltage is less than 30V, a 30-V rated Schottky diode not smaller than SOD-323 package is recommended as boost diode, so the BSW voltage stress from the diode reverse recovery effect can be avoided when the converter operates in short-duration CCM. |
| BIN | 22 | I | Boost converter input pin. For a wide output voltage application, when the boost converter is needed to improve the converter efficiency, BIN is connected to the rectified auxiliary-winding voltage. A 33-µF energy storage capacitor in parallel with a 10-µF ceramic capacitor is recommended. The 33-µF capacitor should be placed close to the auxiliary rectification diode and the auxiliary-winding ground terminal to minimize the rectification switching loop. The 10-µF cap can be placed close to the boost inductor and BGND pin to minimize the boost input switching loop. Together with a Schottky-type auxiliary diode in a SOD-123 package, less than 0.1-Ω winding resistance on the auxiliary winding is required to ensure the boost converter receives sufficient transformer energy under a very low output voltage condition, especially for the 3.3-V to 21-V output range. A small unidirectional 24-V TVS between BIN and AGND can protect the pin from exceeding its 30-V rating, when potential abnormal voltage stress occurs. If the boost converter is not needed, BIN and BSW should be connected to BGND pin. |
| VS | 23 | I | This voltage-sensing input pin is coupled to an auxiliary winding of the converter’s transformer via a resistor divider. The pin and the associated external resistors are used to monitor the output and input voltages and switching edges of the converter at different moments within each switching cycle. The parasitic capacitance between this pin and AGND needs to be minimized to avoid the impact on the output voltage sensing and the dead-time calculation. |
| SET | 24 | I | This pin is used to configure the controller to be optimized for gallium nitride (GaN) power FETs or silicon (Si) power FETs on the primary side. Depending on the setting, it will optimize parameters of the ZVS control loop, dead-time adjustment, and protection features. When pulled high to REF pin, it is optimized for Si FETs. When pulled low to AGND, it is optimized for GaN FETs. |
| EP | 25 | G | The thermal pad must be connected to AGND. |