JAJSJ67 データシート

JAJSJ67E may 2020 – july 2023 UCC28782

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8.4.1 Adaptive ZVS Control with Auto-Tuning

Figure 8-18 shows the simplified block diagram explaining the ZVS control of UCC28782. A high-voltage sensing network provides a replica of the switch node voltage waveform (V_SW) with a limited “visible” lower voltage range that the SWS pin can handle. The ZVS discriminator identifies the ZVS condition and determines the adjustment direction for the on-time of PWMH (t_DM) by detecting if V_SW reaches a predetermined ZVS threshold, V_TH(SWS), within t_Z, where t_Z is the targeted zero voltage transition time of V_SW controlled by the PWMH-to-PWML dead-time optimizer.

In Figure 8-18, V_SW of the current switching cycle in the dashed line has not reached V_TH(SWS) after t_Z expires. The ZVS discriminator sends a TUNE signal to increase t_DM for the next switching cycle in the solid line, such that the negative magnetizing current (I_M-) can be increased to bring V_SW down to a lower level in the same t_Z. After a few switching cycles, the t_DM optimizer settles and locks into ZVS operation of the low-side switch (Q_L). In steady-state, there is a fine adjustment on t_DM, which is the least significant bit (LSB) of the ZVS tuning loop. This small change of t_DM in each switching cycle is too small to significantly move the ZVS condition away from the desired operating point. Figure 8-19 demonstrates how fast the ZVS control can lock into ZVS operation. Before the ZVS loop is settled, UCC28782 starts in a valley-switching mode as t_DM is not long enough to create sufficient I_M-. Within 15 switching cycles, the ZVS tuning loop settles and begins toggling t_DM with an LSB.

Figure 8-18 Block Diagram of Adaptive ZVS Control

Figure 8-19 Auto-Tuning Process of Adaptive ZVS Control

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発注情報

8.4.1 Adaptive ZVS Control with Auto-Tuning