The VDD pin is the primary bias for the internal 5-V REF regulator, internal 13-V P13 regulator, other internal references, and the undervoltage lock-out (UVLO) circuit. As shown in Figure 8-5, the UVLO circuit connected to the VDD pin controls the internal power-path switches among VDD, P13, and SWS pins, in order to allow an external depletion-mode MOSFET (Q_S) to be able to perform both V_VDD startup and switch-node voltage (V_SW) sensing for ZVS control after startup. During startup, SWS and P13 pins are connected to VDD pin allowing Q_S to charge the VDD capacitor (C_VDD) from the V_SW. After VDD startup completes, the ZVS discriminator block and switching logic are enabled. Then, the transformer starts delivering energy to the output capacitor (C_O) every switching cycle, so both output voltage (V_O) and auxiliary winding voltage (V_AUX) increase. As V_AUX is high enough, the auxiliary winding will take over to power V_VDD. The UVLO circuit provides a turn-on threshold of V_VDD(ON) at 17 V and turn-off threshold of V_VDD(OFF) at 10.6 V. For fixed output voltage ACF converter designs, the wide V_VDD range can accommodate lower values of VDD capacitor (C_VDD) and support shorter power-on delays. For ACF designs requiring wide output voltage range, the integrated switching regulator converts the rectified V_AUX to an 18.5-V regulation level of V_VDD. Compared with the conventional bias approach with a high-voltage linear regulator and multiple auxiliary windings, the footprint and conversion efficiency of the integrated switching regulator are improved greatly. For a wide-output design using the bias regulator, a 10 to 15-µF ceramic VDD capacitor is recommended to hold up V_VDD during soft start and to provide decoupling for the regulator switching loop. Section 8.4.10 of this datasheet describes the details on the startup sequencing with the switching regulator.

For a fixed output voltage design, both the BIN and BSW pins should be shorted to BGND, and the rectified V_AUX is directly connected to the VDD pin. As V_VDD reaches V_VDD(ON), the SWS pin is disconnected from the VDD pin by the internal power path switch, so the C_VDD size has to be sufficient to hold V_VDD higher than V_VDD(OFF) until the positive auxiliary winding voltage is high enough to take over bias power delivery during V_O soft start. Therefore, the calculation of minimum capacitance (C_VDD(MIN)) needs to consider the discharging effect from the sink current of the UCC28782 during switching in its run state (I_RUN(SW)), the average operating current of driver (I_DR), and the average gate charge current of half-bridge FETs (I_Qg) throughout the longest time of V_O soft start (t_SS(MAX)).

Equation 5.

t_SS(MAX) estimation should consider the averaged soft-start current (I_SEC(SS)) on the secondary side of ACF, the constant-current output load (I_O(SS)) (if any), maximum output capacitance (C_O(MAX)), and a 0.7-ms time-out potentially being triggered in the startup sequence. 1 ms is applied in the equation to be the worst-case condition of the 0.7-ms timer.

Equation 6.

During V_O soft start, V_CST reaches the maximum current threshold on the CS pin (V_CST(MAX)) , so I_SEC(SS) at the minimum voltage of the input bulk capacitor (V_BULK(MIN)) can be approximated as:

Equation 7.

where R_CS is the current sense resistor, N_PS is primary-to-secondary turns ratio, and V_F is the forward voltage drop of the secondary rectifier.