SLUSC05D July 2014 – May 2016 UCC28880
PRODUCTION DATA.
The UCC28880 can be used in various application topologies with direct or isolated feedback. The device can be used in low-side buck, where the output voltage is negative, or as a low-side buck-boost configuration, where the output voltage is positive. In both configurations the common reference node is the positive input node (VIN+). The device can also be configured as a LED driver in either of the above mentioned configurations. If the application requires the AC-to-DC power supply output to be referenced to the negative input node (VIN-), the UCC28880 can also be configured as a traditional high-side buck as shown in Figure 19. In this configuration, the voltage feedback is sampling the output voltage VOUT, making the DC regulation less accurate and load dependent than in low-side buck configuration, where the feedback is always tracking the VOUT. However, high-conversion efficiency can still be obtained.
Figure 16 shows a typical application example of a non-isolated power supply, where the UCC28880 is connected in a low-side buck configuration having an output voltage that is negative with respect to the positive input voltage (VIN+). The output voltage is set to 12 V in this example, but can easily be changed by changing the value of RFB1. This application can be used for a wide variety of household appliances and automation, or any other applications where mains isolation is not required.
DESCRIPTION | MIN | MAX | UNIT | |
---|---|---|---|---|
DESIGN INPUT | ||||
VIN | AC input voltage | 85 | 265 | VRMS |
fLINE | Line frequency | 47 | 63 | Hz |
IOUT | Output current | 0 | 100 | mA |
DESIGN REQUIREMENTS | ||||
PNL | No-load input power | 50 | mW | |
VOUT | Output voltage | 12 | 13 | V |
ΔVOUT | Output voltage ripple | 350 | mV | |
η | Converter efficiency | 68% |
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Capacitors C1 and C2 in the EMI filter also acts as storage capacitors for the high-voltage input DC voltage (VIN). The required input capacitor size can be calculated according Equation 2.
where
CBULK(min) = 6.96 μF. Considering that electrolytic capacitors, generally used as bulk capacitor, have 20% of tolerance in value, the minimum nominal value required for CBULK is:
Select C1 and C2 to be 4.7 μF each (CBULK = 4.7 μF + 4.7 μF = 9.4 μF > CBULKn(min)).
By using a full-wave rectifier allows a smaller capacitor for C1 and C2, almost 50% smaller.
Capacitor CVDD acts as the decoupling capacitor and storage capacitor for the internal regulator. A 100-nF, 10-V rated ceramic capacitor is enough for proper operation of the device's internal LDO.
The freewheeling diode has to be rated for high-voltage with as short as possible reverse-recovery time (trr).
The maximum reverse voltage that the diode should experience in the application, during normal operation, is given by Equation 4.
A margin of 20% is generally considered.
The use of a fast recovery diode is required for the buck-freewheeling rectifier. When designed in CCM, the diode reverse recovery time should be less than 35 ns to keep low reverse recovery current and the switching loss. For example, STTH1R06A provides 25-ns reverse recovery time. When designed in DCM, slower diode can be used, but the reverse recovery time should be kept less than 75 ns. MURS160 can fit the requirement.
The value of the output capacitor impacts the output ripple. Depending on the combination of capacitor value and equivalent series resistor (RESR). A larger capacitor value also has an impact on the start-up time. For a typical application, the capacitor value can start from 47 μF, to hundreds of μF. A guide for sizing the capacitor value can be calculated by the following equations:
Take into account that both CL and RESR contribute to output voltage ripple. A first pass capacitance value can be selected and the contribution of CL and RESR to the output voltage ripple can be evaluated. If the total ripple is too high the capacitance value has to increase or RESR value must be reduced. In the application example CL was selected (47 µF) and it has an RESR of 0.3 Ω. So the RESR contributes for 1/3 of the total ripple. The formula that calculates CL is based on the assumption that the converter operates in burst of four switching cycles. The number of bursts per cycle could be different, the formula for CL is a first approximation.
The resistor should be chosen so that the output current in any standby/no-load condition is higher than the leakage current through the integrated power MOSFET. If the standby load current is ensured to always be larger than the specified ILEAKAGE, the RL is not needed. If OVP protection is required for safety reasons, then a zener could be placed across the output (not fitted in the application example). In the application example RL = 402 kΩ. This ensures a minimum load current of at least ~30 µA when VOUT = 12 V.
Initial calculations:
Half of the peak-to-peak ripple current at full load:
When operating in DCM, the peak-to-peak current ripple is the peak current of the device.
Average MOSFET conduction minimum duty cycle at continuous conduction mode is:
If the converter operates in discontinuous conduction mode:
Maximum allowed switching frequency at VIN(max) and full load:
Switching frequency has a maximum value limit of fSW(max).
The worst case ILIMIT = 140 mA, but assuming ΔIL = 100 mA.
The converter works in continuous conduction mode (ΔIL < ILIMIT) so the
The maximum allowed switching frequency is 61.7 kHz because the calculated value exceeds it.
The duty cycle does not force the MOSFET on time to go below tON_TO. If DMIN/TON_TO < fSW(max), the switching frequency is reduced by current runaway protection and the maximum average switching frequency is lower than fSW(max), the converter can't support full load.
The minimum inductance value satisfies both the following conditions:
In the application example, 2.2 mH is selected as the minimum standard value that satisfy Equation 13 and Equation 14. The value of Equation 14 can be found by characterization graph of Figure 10. Pick the value at the desired maximum junction temperature.
The feedback path of Q1, RFB1 and RFB2 implements a level-shifted direct feedback. RFB2 sets the current through the feedback path, and RFB1 sets the output voltage. Q1 acts as the level shifter and needs to be rated for high voltage. The output voltage is determined as follows:
where
For the application example a target of ~20-μA of current is selected through the external feedback path (IFB).
Choose a standard resistor size for RFB2 = 51 kΩ. For the high-voltage PNP transistor choose a 500-V rated transistor with a VBE ≈ 0.5 V for the feedback current. To achieve the 12-V output voltage RFB1 needs to be:
Choose a standard resistor size for RFB1 = 591 kΩ.
To change the output voltage, change the value for RFB1. For example, to target a 5-V output voltage, RFB1 should be changed to a 230-kΩ resistor.
Accuracy of the output-voltage level depends proportionally on the variation of VFB_TH, and on the absolute accuracy of VBE according to Equation 16 and Equation 17.
The current through the feedback path is connected over the high voltage input (VIN), and this feedback current is always on. Higher current provides less noise-sensitive feedback, the feedback current should be minimized in order to minimize the total power consumption.
Figure 17 shows the efficiency diagram of the converter, a design previous discussed. Figure 18 shows the output voltage vs output current diagram. The two diagrams were obtained by measuring efficiency (Figure 17), output current and output voltage (Figure 18) moving resistive load value from infinite (load disconnected) up to zero (output shorted). The different curves of the diagram correspond to different AC input voltage.
Table 3 shows converter efficiency. Table 4 shows the converter input power in no-load conditions and output shorted conditions. The no-load condition shows the converter stand-by performance.
VIN_AC (VRMS) | LOAD (mA) | EFFICIENCY (%) | AVERAGE EFFICIENCY (%) |
---|---|---|---|
115 | 25 | 80.3 | 81.3 |
50 | 81.4 | ||
75 | 81.6 | ||
100 | 81.9 | ||
230 | 25 | 78.5 | 81.2 |
50 | 81.1 | ||
75 | 82.1 | ||
100 | 82.7 |
VIN (VRMS) | NO LOAD PIN (mW) | OUTPUT SHORTED PIN (mW) | OUTPUT SHORTED IOUT (mA) |
---|---|---|---|
85 | 16 | 453 | 214 |
115 | 19.5 | 435 | 213 |
140 | 22.5 | 417 | 211 |
170 | 26 | 443 | 213 |
230 | 33 | 430 | 209 |
265 | 37.5 | 344 | 182 |
Figure 19 shows a typical application example of a non-isolated power supply, where the UCC28880 is connected in a high-side buck configuration having an output voltage that is positive with respect to the negative high-voltage input (VIN-).
DESCRIPTION | MIN | MAX | UNIT | |
---|---|---|---|---|
DESIGN INPUT | ||||
VIN | AC input Voltage | 85 | 265 | VRMS |
fLINE | Line frequency | 47 | 63 | Hz |
IOUT | Output current | 0 | 100 | mA |
DESIGN REQUIREMENTS | ||||
PNL | No-load input power | 50 | mW | |
VOUT | Output voltage | 12 | 14 | V |
ΔVOUT | Output voltage ripple | 250 | mV | |
η | Converter efficiency | 68% |
The low-side buck converter and high-side buck converter design procedures are very similar.
In low-side buck converter the output voltage is always sensed by the FB pin and UCC28880 internal controller can turn on the MOSFET on VOUT. In high-side buck converter applications the information on the output voltage value is stored on CFB capacitor. This information is not updated in real time. The information on CFB capacitor is updated just after MOSFET turn-off event. When the MOSFET is turned off, the inductor current forces the freewheeling diode (D1 in Figure 19) to turn on and the GND pin of UCC28880 goes negative at -Vd1 (where Vd1 is the forward drop voltage of diode D1) with respect to the negative terminal of bulk capacitor (C1 in Figure 19). When D1 is on, through diode D4, the CFB capacitor is charged at VOUT – Vd4 + Vd1. Set the output voltage regulation level using Equation 18.
where
The time constant selection leads to a slight output-voltage increase in no-load or light-load conditions. In order to reduce the output-voltage increase, increase τFB. The drawback of increasing τFB is t in high-load conditions VOUT could drop.
Figure 20 shows the output voltage vs output current. Different plots correspond to different converter AC input voltages. Figure 21 shows efficiency changes vs output power. Different plots correspond to different converter AC input voltages.
VIN_AC (VRMS) | LOAD (mA) | EFFICIENCY (%) | AVERAGE EFFICIENCY (%) |
---|---|---|---|
115 | 25 | 75.2 | 76.8 |
50 | 77.1 | ||
75 | 77.6 | ||
100 | 77.7 | ||
230 | 25 | 72.6 | 74.8 |
50 | 75.1 | ||
75 | 75.7 | ||
100 | 76.3 |
VIN (VRMS) | NO LOAD PIN (mW) | OUTPUT SHORTED PIN (mW) | OUTPUT SHORTED IOUT (mA) |
---|---|---|---|
85 | 31 | 415 | 212 |
115 | 34 | 399 | 209 |
140 | 36 | 414 | 211 |
170 | 38 | 401 | 208 |
230 | 44 | 394 | 195 |
265 | 47 | 333 | 174 |
Features include:
Features include:
Features Include:
Features include:
Features include: