JAJSG35B August   2018  – October 2024 UCC28950 , UCC28951

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.7 Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)

The resistor REF from the DELEF pin to GND along with the resistor divider RAEFHI from CS pin to ADELEF pin and RAEF from ADELEF pin to GND sets equal delays TAFSET and TBESET between outputs OUTA or OUTB going low and related output OUTF or OUTE going low Figure 6-4. The total resistance of this resistor divider should be in the range between 10kΩ and 20kΩ.

UCC28950 UCC28951 Delay Definitions Between OUTA and OUTF, OUTB and OUTE Figure 6-4 Delay Definitions Between OUTA and OUTF, OUTB and OUTE

These delays gradually increase as function of the CS signal from TAFSET1, which is measured at VCS = 0.2V, to TAFSET2, which is measured at VCS = 1.8V. This is opposite to the DELAB and DELCD behavior and this delay is longest (TAFSET2) when the signal at CS pin is maximized and shortest (TAFSET1) when the CS signal is minimized. This approach will reduce the synchronous rectifier MOSFET body diode conduction time over a wide load current range thus improving efficiency. The ratio between the longest and shortest delays is set by the resistor divider RAEFHI and RAEF. If CS and ADELEF are tied, the ratio is maximized. If ADELEF is connected to GND, then the delay is fixed, defined only by resistor REF from DELEF to GND.

The delay time TAFSET is defined by the following Equation 6. Equation 6 also defines the delay time TBESET.

Equation 6. T A F S E T = T B E S E T = R E F × 5 V - C S × K E F × 0.993 + 2.063 V × 1 p F - 1.3 n s

where

  • the CS, which is the voltage at pin CS, is in volts
  • KEF is a numerical gain factor of CS voltage from 0 to 1

Equation 7 is an empirical approximation of measured data, thus, there is no unit agreement in it. As an example, assume REF = 15kΩ, CS = 1V and KEF = 0.5. Then the TAFSET is going to be 41.7ns. KEF is defined as Equation 7:

Equation 7. UCC28950 UCC28951

RAEF and RAEFHI define the portion of voltage at pin CS applied to the pin ADELEF (see Figure 7-3). KEF defines how significantly the delay time depends on CS voltage. KEF varies from 0, where ADELEF pin is shorted to ground (RAEF = 0) and the delay does not depend on CS voltage, to 1, where ADELEF is tied to CS (RAEFHI = 0).

Note:

The allowed resistor range on DELEF, REF is 13kΩ to 90kΩ.

The plots in Figure 6-5 and Figure 6-6 show delay time settings as function of CS voltage and KEF for two different conditions: REF = 13kΩ (Figure 6-5) and REF = 90kΩ (Figure 6-6)

UCC28950 UCC28951 Delay Time TAFSET and TBESET (Over CS Voltage and Selected KEF for REF Equal 13kΩ)Figure 6-5 Delay Time TAFSET and TBESET (Over CS Voltage and Selected KEF for REF Equal 13kΩ)
UCC28950 UCC28951 Delay Time TAFSET and TBESET (Over CS Voltage and Selected KEF for REF Equal 90kΩ)Figure 6-6 Delay Time TAFSET and TBESET (Over CS Voltage and Selected KEF for REF Equal 90kΩ)