JAJSG35B August   2018  – October 2024 UCC28950 , UCC28951

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Timing Requirements

MINNOMMAXUNIT
CYCLE-BY-CYCLE CURRENT LIMIT
TCSPropagation delay from CS to OUTC and OUTD outputs
Input pulse between CS and GND from zero to 2.5 V		100ns
PROGRAMMABLE DELAY TIME SET ACCURACY AND RANGE(1)(1)(1)(1)(1)
TABSET1Short delay time set accuracy between OUTA and OUTB
CS = ADEL = ADELEF = 1.8 V		324556ns
TABSET2Long delay time set accuracy between OUTA and OUTB
CS = ADEL = ADELEF = 0.2 V		216270325ns
TCDSET1Short delay time set accuracy between OUTC and OUTD
CS = ADEL = ADELEF = 1.8 V		324556ns
TCDSET2Long delay time set accuracy between OUTC and OUTD
CS = ADEL = ADELEF = 0.2 V		216270325ns
TAFSET1Short delay time set accuracy between falling OUTA, OUTF
CS = ADEL = ADELEF = 0.2 V		223548ns
TAFSET2Long delay time set accuracy between falling OUTA, OUTF
CS = ADEL = ADELEF = 1.8 V		190240290ns
TBESET1Short delay time set accuracy between falling OUTB, OUTE
CS = ADEL = ADELEF = 0.2 V		223548ns
TBESET2Long delay time set accuracy between falling OUTB, OUTE
CS = ADEL = ADELEF = 1.8 V		190240290ns
ΔTADBCPulse matching between OUTA rise, OUTD fall and OUTB rise, OUTC fall
CS = ADEL = ADELEF = 1.8 V, COMP = 2 V		–50050ns
ΔTABBAHalf cycle matching between OUTA rise, OUTB rise and OUTB rise, OUTA rise
CS = ADEL = ADELEF = 1.8 V, COMP = 2 V		–50050ns
ΔTEEFFPulse matching between OUTE fall, OUTE rise and OUTF fall, OUTF rise
CS = ADEL = ADELEF = 0.2 V, COMP = 2 V		–60060ns
ΔTEFFEPulse matching between OUTE fall, OUTF rise and OUTF fall, OUTE rise
CS = ADEL = ADELEF = 0.2 V, COMP = 2 V		–60060ns
LIGHT-LOAD EFFICIENCY CIRCUIT
TMINTotal range, RTMIN = 88.7 kΩ425525625ns
OUTPUTS OUTA, OUTB, OUTC, OUTD, OUTE, OUTF
TRRise time, CLOAD = 100 pF925ns
TFFall time, CLOAD = 100 pF725ns