JAJSG35A august 2018 – december 2021 UCC28951
PRODUCTION DATA
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ADEL | 14 | I | Dead-time programming for the primary switches over CS voltage range, tABSET and tCDSET. |
ADELEF | 13 | I | Delay-time programming between primary side and secondary side switches, tAFSET and tBESET. |
COMP | 4 | I/O | Error amplifier output and input to the PWM comparator. |
CS | 15 | I | Current sense for cycle-by-cycle overcurrent protection and adaptive delay functions. |
DCM | 12 | I | DCM threshold setting. |
DELAB | 6 | I | Dead-time delay programming between OUTA and OUTB. |
DELCD | 7 | I | Dead-time delay programming between OUTC and OUTD. |
DELEF | 8 | I | Delay-time programming between OUTA to OUTF, and OUTB to OUTE. |
EA+ | 2 | I | Error amplifier noninverting input. |
EA– | 3 | I | Error amplifier inverting input. |
GND | 24 | — | Ground. All signals are referenced to this node. |
OUTA | 22 | O | 0.2-A sink and source primary switching output. |
OUTB | 21 | O | |
OUTC | 20 | O | |
OUTD | 19 | O | |
OUTE | 18 | O | |
OUTF | 17 | O | |
RSUM | 11 | I | Slope compensation programming. Voltage mode or peak current mode setting. |
RT | 10 | I | Oscillator frequency set. leader or follower mode setting. |
SS/EN | 5 | I | Soft-start programming, device enable and hiccup mode protection circuit. |
SYNC | 16 | I/O | Synchronization out from leader controller to input of follower controller. |
TMIN | 9 | I | Minimum duty cycle programming in burst mode. |
VDD | 23 | I | Bias supply input. |
VREF | 1 | O | 5-V, ±1.5%, 20-mA reference voltage output. |