JAJSOA1C June   2022  – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
        2. 9.2.2.2  Primary Magnetizing Inductance of the Flyback Transformer (LM)
        3. 9.2.2.3  Number of Turns of the Flyback Transformer Windings
        4. 9.2.2.4  Current Sense Resistors (R24, R25) and Current Limiting
        5. 9.2.2.5  Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
        6. 9.2.2.6  Primary-Side Current Stress and Input Capacitor Selection
        7. 9.2.2.7  Secondary-Side Current Stress and Output Capacitor Selection
        8. 9.2.2.8  VDD Capacitors (C12, C18)
        9. 9.2.2.9  Gate Drive Network (R14, R16, Q6)
        10. 9.2.2.10 VREF Capacitor (C18)
        11. 9.2.2.11 RT/CT Components (R12, C15)
        12. 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
        13. 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
        14. 9.2.2.14 Voltage Feedback Compensation
          1. 9.2.2.14.1 Power Stage Gain, Poles, and Zeroes
          2. 9.2.2.14.2 Compensation Components
          3. 9.2.2.14.3 Bode Plots and Stability Margins
          4. 9.2.2.14.4 Stability Measurements
      3. 9.2.3 Application Curves
    3. 9.3 PCB Layout Recommendations
      1. 9.3.1 PCB Layout Routing Examples
    4. 9.4 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4 Power Supply Recommendations

The absolute maximum supply voltage is 30 V, including any transients that may be present. If this voltage is exceeded, device damage is likely. Thus, the supply pin must be decoupled as close to the GND pin as possible. Also, because no clamp is included in the device, the supply pin must be protected from external sources which could exceed the 30-V level.

To prevent false triggering due to leading edge noises, an RC current sense filter may be required on CS. Keep the time constant of the RC filter well below the minimum on-time pulse width.

To prevent noise problems with high-speed switching transients, bypass VREF to ground with a ceramic capacitor close to the device package. A minimum of 0.1-µF ceramic capacitor is required. Additional VREF bypassing is required for external loads on the reference. An electrolytic capacitor may also be used in addition to the ceramic capacitor.