JAJSOA1C June   2022  – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
        2. 9.2.2.2  Primary Magnetizing Inductance of the Flyback Transformer (LM)
        3. 9.2.2.3  Number of Turns of the Flyback Transformer Windings
        4. 9.2.2.4  Current Sense Resistors (R24, R25) and Current Limiting
        5. 9.2.2.5  Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
        6. 9.2.2.6  Primary-Side Current Stress and Input Capacitor Selection
        7. 9.2.2.7  Secondary-Side Current Stress and Output Capacitor Selection
        8. 9.2.2.8  VDD Capacitors (C12, C18)
        9. 9.2.2.9  Gate Drive Network (R14, R16, Q6)
        10. 9.2.2.10 VREF Capacitor (C18)
        11. 9.2.2.11 RT/CT Components (R12, C15)
        12. 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
        13. 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
        14. 9.2.2.14 Voltage Feedback Compensation
          1. 9.2.2.14.1 Power Stage Gain, Poles, and Zeroes
          2. 9.2.2.14.2 Compensation Components
          3. 9.2.2.14.3 Bode Plots and Stability Margins
          4. 9.2.2.14.4 Stability Measurements
      3. 9.2.3 Application Curves
    3. 9.3 PCB Layout Recommendations
      1. 9.3.1 PCB Layout Routing Examples
    4. 9.4 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1 PCB Layout Routing Examples

1) The power ground should not disturb (i.e. mix with) the signal ground. The signal ground includes the small R’s and C’s around the controller (for COMP, FB, RT/CT, CS) and the controller ground pin. The power ground includes the input capacitors, current sense resistors, return for the Y-capacitor, and gate drive return via the PNP transistor Q6.

GUID-20221021-SS0I-DK9T-CT0J-BWJDBMZNQC2K-low.png Figure 9-22 Top Layer: Signal Grounds, Power Grounds, and their Connection to a Single-Point Ground
GUID-20221021-SS0I-JL03-DSBW-ZFFK01VKS8D4-low.png Figure 9-23 Bottom Layer: Signal Grounds, Power Grounds, and their Connection to a Single-Point Ground

2) The primary-side power loop must be minimized. Use relatively wide traces. This loop includes the input capacitors (C2, C3), transformer primary winding (T1 pins 1, 3), switching MOSFET (Q5), and sense resistors (R24, R25). Do not use vias in this path.

GUID-20221021-SS0I-GF1S-61JG-8VLPWSH8CQWF-low.png Figure 9-24 Primary-Side Power Loop Routing

3) The secondary-side power loop should be minimized. Use copper pours or very wide traces. This loop includes the output capacitors (C9, C10), transformer secondary winding (T1 pins 8/9, 10/11), and output rectifier diode (D11). If interconnection between layers is required use multiple vias to handle the high peak currents.

GUID-20221021-SS0I-F4BM-373M-G78XKCDDBGFP-low.png Figure 9-25 Secondary-Side Power Loop Routing

4) The AUX feedback loop should be minimized. This loop includes components C13, D13, and the transformer AUX winding (T1 pins 6, 5).

GUID-20221021-SS0I-M52N-5DSC-ZFBQ9FPVXPJH-low.png Figure 9-26 AUX Feedback Loop Routing

5) The loop of the high-voltage clamp must be minimized. This loop includes D1, D3, R2//R28, and D7. All these components should be on the same layer.

GUID-20221021-SS0I-P1ZG-GKBV-WJZSR9GVDSRW-low.png Figure 9-27 High-Voltage Clamp Loop Routing

6) The Y-type capacitor from the isolation ground to the power ground (C14, C24) should route back to the single point ground without disturbing the signal ground around the controller.

GUID-20221021-SS0I-VJTM-PJFC-KHKBKC7WM4TZ-low.png Figure 9-28 Y-Capacitor Ground Routing

7) The trace from the OUT pin (U1 pin 6) to the gate of the switching MOSFET (Q5-1) must be as short as possible and relatively wide. Do not use vias in this path.

GUID-20221021-SS0I-JZ2W-0LRD-DXDF0HGXFPH0-low.png Figure 9-29 Gate Drive (OUT) Trace Routing

8) The collector of the PNP gate pull-down transistor (Q6 pin 3) should route directly back to the single point ground without disturbing the signal ground around the controller.

GUID-20221021-SS0I-WDNH-Z0X9-Q7RCPQQQ7MR7-low.png Figure 9-30 Gate Pull-Down PNP Transistor Collector Routing

9) The connection from the current sense resistors (R24/R25) to the low-pass filter (R21, C22) and on to the CS pin must be direct and it must avoid noisy signals. For example, do not route this trace near the MOSFET gate drive or SW node.

GUID-20221021-SS0I-MPZD-LPPG-LV6H0WTS8NHR-low.png Figure 9-31 Current Sense Trace Routing

10) The loop formed by the R-C snubber (R4, C5) around the output rectifier diode (D11) should be minimized. Do not use vias in this path.

11) The VDD pin must have a ceramic capacitor (C18) located as close as possible.

12) The VREF pin must have a ceramic capacitor (C16) located as close as possible.

13) The compensation components (R18, C19, C20) must be located near the COMP pin.

14) The feedback divider components (R17, R19, R20) must be located near the FB pin.

15) The frequency setting components (R12, C15) must be located near the RT/CT pin.