JAJSOA1C June   2022  – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
        2. 9.2.2.2  Primary Magnetizing Inductance of the Flyback Transformer (LM)
        3. 9.2.2.3  Number of Turns of the Flyback Transformer Windings
        4. 9.2.2.4  Current Sense Resistors (R24, R25) and Current Limiting
        5. 9.2.2.5  Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
        6. 9.2.2.6  Primary-Side Current Stress and Input Capacitor Selection
        7. 9.2.2.7  Secondary-Side Current Stress and Output Capacitor Selection
        8. 9.2.2.8  VDD Capacitors (C12, C18)
        9. 9.2.2.9  Gate Drive Network (R14, R16, Q6)
        10. 9.2.2.10 VREF Capacitor (C18)
        11. 9.2.2.11 RT/CT Components (R12, C15)
        12. 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
        13. 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
        14. 9.2.2.14 Voltage Feedback Compensation
          1. 9.2.2.14.1 Power Stage Gain, Poles, and Zeroes
          2. 9.2.2.14.2 Compensation Components
          3. 9.2.2.14.3 Bode Plots and Stability Margins
          4. 9.2.2.14.4 Stability Measurements
      3. 9.2.3 Application Curves
    3. 9.3 PCB Layout Recommendations
      1. 9.3.1 PCB Layout Routing Examples
    4. 9.4 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VVDD = 20 V (1)(for UCC28C56H/L-Q1, UCC28C57H/L-Q1 and UCC28C58/9-Q1), VVDD = 15 V(1) (for the rest), RRT = 10 kΩ, CCT = 3.3 nF, CVDD = 0.1 µF and no load on the outputs, TJ = –40°C to 150°C (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
REFERENCE
VVREFVREF voltage, initial accuracyIOUT = 1 mA4.9555.05V
Line regulationVVDD = 12 V to 25 V0.220mV
Load regulation1 mA to 20 mA325mV
Temperature stabilitySee (2)0.20.4mV/°C
Total output variationSee (2)4.825.18V
VREF noise voltage10 Hz to 10 kHz, TJ = 25°C, see (2)50µV
Long term stability1000 hours, TJ = 150°C, see (2)525mV
IVREFOutput short circuit (source current)304555mA
OSCILLATOR
fOSCInitial accuracyTJ = 25°C, see (3)50.55355kHz
TJ = Full Range, see (3)50.557kHz
Voltage stability12 V ≤ VVDD ≤ 25 V0.2%1%
Temperature stabilityTJ(MIN) to TJ(MAX), see (2)1%2.5%
AmplitudeRT/CT pin peak-to-peak voltage1.9V
Discharge currentTJ = 25°C, VRT/CT = 2 V, see (4)7.78.49mA
TJ = Full Range, VRT/CT = 2 V, see (4)7.28.49.5
ERROR AMPLIFIER
VFBFeedback input voltage, initial accuracyTJ = 25°C, VCOMP = 2.5 V2.4752.52.525V
Feedback input voltage, total variationTJ = Full Range, VCOMP = 2.5 V2.452.52.55V
IFBInput bias currentVFB = 5 V, (sourcing current)0.12µA
AVOLOpen-loop voltage gain2 V ≤ VOUT ≤ 4 V6590dB
Unity gain bandwidthSee (2)11.5MHz
PSRRPower supply rejection ratio12 V ≤ VVDD ≤ 25 V60dB
Output sink currentVFB = 2.7 V, VCOMP = 1.1 V214mA
Output source currentVFB = 2.3 V, VCOMP = 5 V, (sourcing current)0.51mA
VOHHigh-level COMP voltageVFB = 2.7 V, RCOMP = 15 kΩ COMP to GNDVREF–0.2V
VOLLow-level COMP voltageVFB = 2.7 V, RCOMP = 15 kΩ COMP to VREF0.11.1V
CURRENT SENSE
ACSGainTJ = 25°C, See (5)2.8533.15V/V
TJ = Full Range, See (5)2.7533.15V/V
VCSMaximum input signalVFB < 2.4 V0.911.1V
PSRRPower supply rejection ratioVVDD = 12 V to 25 V(2)(5)70dB
ICSInput bias current (source current)0.12µA
tDCS to output delay3570ns
COMP to CS offsetVCS = 0 V1.15V
OUTPUT
VOUT(low)RDS(on) pulldownISINK = 200 mA5.515Ω
VOUT(high)RDS(on) pullupISOURCE = 200 mA1025Ω
tRISERise tImeTJ = 25°C, COUT = 1 nF2550ns
tFALLFall tImeTJ = 25°C, COUT = 1 nF2040ns
UNDERVOLTAGE LOCKOUT
VDDONStart threshold(6)UCC28C52-Q1, UCC28C54-Q113.514.515.5V
UCC28C53-Q1, UCC28C55-Q17.88.49
UCC28C50-Q1, UCC28C51-Q16.577.5

UCC28C56H-Q1, UCC28C57H-Q1

17.6

18.8

20

UCC28C56L-Q1, UCC28C57L-Q1

17.6

18.8

20

UCC28C58-Q1, UCC28C59-Q1

14.8

16

17.2

VDDOFFMinimum operating voltage (6)UCC28C52-Q1, UCC28C54-Q18910V
UCC28C53-Q1, UCC28C55-Q177.68.2
UCC28C50-Q1, UCC28C51-Q16.16.67.1
UCC28C56H-Q1, UCC28C57H-Q1

15

15.5

16

UCC28C56L-Q1, UCC28C57L-Q1

13.95

14.5

15

UCC28C58-Q1, UCC28C59-Q1

12

12.5

13

VDDHystVDDON - VDDOFF(6)

UCC28C52-Q1, UCC28C54-Q1

5.4

5.5

V

UCC28C53-Q1, UCC28C55-Q1

0.8

0.9

UCC28C51-Q1, UCC28C50-Q1

0.4

0.5

UCC28C56H-Q1, UCC28C57H-Q1

2.6

3.3

UCC28C56L-Q1, UCC28C57L-Q1

3.65

4.3

UCC28C58-Q1, UCC28C59-Q1

2.8

3.5

PWM
DMAXMaximum duty cycleUCC28C52-Q1, UCC28C53-Q1, UCC28C50-Q1, VFB < 2.4 V94%96%
UCC28C56H-Q1, UCC28C56L-Q1, UCC28C58-Q1, VFB < 2.4 V
UCC28C54-Q1, UCC28C55-Q1, UCC28C51-Q1, VFB < 2.4 V47%48%
UCC28C57H-Q1, UCC28C57L-Q1, UCC28C59-Q1, VFB < 2.4 V
DMINMinimum duty cycleVFB > 2.6 V0%
CURRENT SUPPLY
ISTART-UPStart-up currentVVDD = VDDON – 0.5 V50

75

µA
IVDDOperating supply currentVFB = VCS = 0 V1.3

2

mA
(1) Adjust VVDD above the start threshold before setting at 20 V for UCC28C56H/L-Q1, UCC28C57H/L-Q1 and UCC28C58/9-Q1, and 15.5 V for the rest family.
(2) Ensured by design. Not production tested.
(3) Output frequencies of the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1, and the UCC28C59-Q1 are half the oscillator frequency.
(4) Oscillator discharge current is measured with RRT = 10 kΩ to VREF.
(5) Parameter measured at trip point of latch with VFB = 0 V. Gain is defined as ACS = ΔVCOMP / ΔVCS , 0 V ≤ VCS ≤ 900 mV.
(6) VDDON, VDDOFF, and VREF are tracking each other in the same direction, e.g., min VDDOFF is due to min VDDON.