SLUSFZ0 November   2024 UCC33411-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Safety-Related Certifications
    7. 6.7 Electrical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 Output Voltage Soft-Start
      3. 7.3.3 Output Voltage Steady-State Regulation
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Input Under-Voltage and Over-Voltage Lockout
        2. 7.3.4.2 Output Under-Voltage Protection
        3. 7.3.4.3 Output Over-Voltage Protection
        4. 7.3.4.4 Over-Temperature Protection
        5. 7.3.4.5 Fault Reporting and Auto-Restart
      5. 7.3.5 VCC Load Recommended Operating Area
      6. 7.3.6 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical and Packaging Information
    1. 13.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DHA|16
サーマルパッド・メカニカル・データ
発注情報

Output Voltage Steady-State Regulation

The UCC33411-Q1 uses hysteritic control to regulate the output voltage between upper and lower bands as shown in Figure 7-4. The regulation block on the secondary side senses the regulated output voltage and sends a feedback signal to the primary side through the inductive communication channel to turn the primary power stage On or Off to maintain the regulated output whithin the hysterisis bands. During steady-state regulation, the burst frequency will change according to the output capacitors and loading conditions. The burst frequency will be highest at higher loading conditions and lowest at light loading conditions by which light load efficiency improvments can be achieved. The Burst-On duration (tON) will increase with heavy loading conditions recommended operating conditions or higher output capacitor values . The UCC33411-Q1 has an overpower protection feature that will limit the maximum tON value to typical of 13us.

The UCC33411-Q1 can program the VCC_REG voltage accoring to the SEL pin connection. The SEL pin voltage is monitored during soft-start sequence when VCC < VVCC_UVLO threshold . The output voltage is then programmed to 3.3V with SEL = VCC or 3.7V with SEL = GNDS. Note that after this initial monitoring, the SEL pin no longer affects the VCC output level. In order to change the output mode selection, either the EN/FLT pin must be toggled or the VINP power supply must be cycled off and back on.

UCC33411-Q1 Output Voltage Hysterisis Mode
            Control Figure 7-4 Output Voltage Hysterisis Mode Control