SLUSFG5 November 2024 UCC33421-Q1
ADVANCE INFORMATION
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PIN | TYPE (1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN/FLT | 1 | I/O |
Multi-function Enable input pin and fault output pin. Connect to microcontroller through an 18kΩ or greater pull-up resistor. Enable input pin: Forcing EN low disables the device. Pull high to enable normal device functionality. Fault output pin: This pin is pulled low for 200μs to alert that power converter is shutdown due to fault condition |
VINP | 2 | P | Primary side input supply voltage pin. 15nF (CIN1) and 10μF (CIN2) ceramic bypass capacitors placed close to device pins are required between VINP and GNDP pins |
3 | |||
GNDP | 4 | G | Power ground return connection for VINP. |
5 | |||
6 | |||
7 | |||
8 | |||
SEL | 9 | I | VCC selection pin. VCC setpoint is 5.0V when SEL is connected to VCC, and 5.5V when SEL is shorted to GNDS |
VCC | 10 | P | Isolated supply output voltage pin. 15nF (COUT1) and 22μF (COUT2) ceramic bypass capacitors placed close to device pins are required between VCC and GNDS pins |
11 | |||
GNDS | 12 | G | Power ground return connection for VCC. |
13 | |||
14 | |||
15 | |||
16 |