SLUS395K February   2000  – October 2015 UCC2817 , UCC2818 , UCC3817 , UCC3818

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference Section and Error Amplifier
      2. 7.3.2 Zero Power Block
      3. 7.3.3 Multiplier
      4. 7.3.4 Output Overvoltage Protection
      5. 7.3.5 Pin Descriptions
        1. 7.3.5.1  CAI
        2. 7.3.5.2  CAOUT
        3. 7.3.5.3  CT
        4. 7.3.5.4  DRVOUT
        5. 7.3.5.5  GND
        6. 7.3.5.6  IAC
        7. 7.3.5.7  MOUT
        8. 7.3.5.8  OVP/EN
        9. 7.3.5.9  PKLMT
        10. 7.3.5.10 RT
        11. 7.3.5.11 SS
        12. 7.3.5.12 VAOUT
        13. 7.3.5.13 VCC
        14. 7.3.5.14 VFF
        15. 7.3.5.15 VSENSE
        16. 7.3.5.16 VREF
    4. 7.4 Device Functional Modes
      1. 7.4.1 Transition Mode Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Stage
          1. 8.2.2.1.1 LBOOST
          2. 8.2.2.1.2 COUT
        2. 8.2.2.2 Softstart
        3. 8.2.2.3 Multiplier
        4. 8.2.2.4 Voltage Loop
        5. 8.2.2.5 Current Loop
        6. 8.2.2.6 Start Up
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Switch Selection
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Capacitor Ripple Reduction
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • N|16
  • DW|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

10.1.1 Capacitor Ripple Reduction

For a power system where the PFC boost converter is followed by a dc-to-dc converter stage, it can be beneficial to synchronize the two converters. In addition to the usual advantages such as noise reduction and stability, proper synchronization can significantly reduce the ripple currents in the output capacitor of the boost circuit. Figure 15 helps illustrate the impact of proper synchronization, by showing a PFC boost converter together with the simplified input stage of a forward converter.

The capacitor current during a single switching cycle depends on the status of the switches Q1 and Q2, and is shown in Figure 16. With a synchronization scheme that maintains conventional trailing-edge modulation on both converters, the capacitor current ripple is highest. The greatest ripple current cancellation is attained when the overlap of Q1 offtime and Q2 ontime is maximized. One method of achieving this is to synchronize the turnon of the boost diode (D1) with the turnon of Q2. This approach implies that the leading edge of the boost converter is pulse-width modulated, while the forward converter is modulated with traditional trailing-edge PWM. The UCC3817 is designed as a leading-edge modulator with easy synchronization to the downstream converter to facilitate this advantage. Table 2 compares the ICB(rms) for D1/Q2 synchronization as offered by UCC3817 versus the ICB(rms) for the other extreme of synchronizing the turnon of Q1 and Q2 for a 200-W power system with a VBST of 385 V.

UCC2817 UCC2818 UCC3817 UCC3818 simp_rep_2-stage_pfc_pwr_supp.gif Figure 15. Simplified Representation of a 2-Stage PFC Power Supply
UCC2817 UCC2818 UCC3817 UCC3818 timing_wvfrm_synch_sch.gif Figure 16. Timing Waveforms for Synchronization Scheme

Table 2. Effects of Synchronization on Boost Capacitor Current

VIN = 85 V VIN = 120 V VIN = 240 V
D(Q2) Q1/Q2 D1/Q2 Q1/Q2 D1/Q2 Q1/Q2 D1/Q2
0.35 1.491 A 0.835 A 1.341 A 0.663 A 1.024 A 0.731 A
0.45 1.432 A 0.93 A 1.276 A 0.664 A 0.897 A 0.614 A

Table 2 illustrates that the boost capacitor ripple current can be reduced by approximately 50% at nominal line, and about 30% at high line with the synchronization scheme facilitated by the UCC3817. Figure 17 shows the suggested technique for synchronizing the UCC3817 to the downstream converter. With this technique, maximum ripple reduction as shown in Figure 16 is achievable. The output capacitance value can be significantly reduced if its choice is dictated by ripple current, or the capacitor life can be increased as a result. In cost-sensitive designs where holdup time is not critical, this is a significant advantage.

An alternative method of synchronization makes it possible to achieve the same ripple reduction. In this method, the turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and maintains trailing edge modulation on both converters, the synchronization is more difficult to achieve, and the circuit can become susceptible to noise as the synchronizing edge itself is being modulated.

UCC2817 UCC2818 UCC3817 UCC3818 synch_ucc3817_to_downstram_conv.gif Figure 17. Synchronizing the UCC3817 to a Down-Stream Converter

10.2 Layout Example

UCC2817 UCC2818 UCC3817 UCC3818 fig2_sluu077.gif Figure 18. UCC3817EVM Evaluation Board Layout Assembly