SLUS395K February   2000  – October 2015 UCC2817 , UCC2818 , UCC3817 , UCC3818

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference Section and Error Amplifier
      2. 7.3.2 Zero Power Block
      3. 7.3.3 Multiplier
      4. 7.3.4 Output Overvoltage Protection
      5. 7.3.5 Pin Descriptions
        1. 7.3.5.1  CAI
        2. 7.3.5.2  CAOUT
        3. 7.3.5.3  CT
        4. 7.3.5.4  DRVOUT
        5. 7.3.5.5  GND
        6. 7.3.5.6  IAC
        7. 7.3.5.7  MOUT
        8. 7.3.5.8  OVP/EN
        9. 7.3.5.9  PKLMT
        10. 7.3.5.10 RT
        11. 7.3.5.11 SS
        12. 7.3.5.12 VAOUT
        13. 7.3.5.13 VCC
        14. 7.3.5.14 VFF
        15. 7.3.5.15 VSENSE
        16. 7.3.5.16 VREF
    4. 7.4 Device Functional Modes
      1. 7.4.1 Transition Mode Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Stage
          1. 8.2.2.1.1 LBOOST
          2. 8.2.2.1.2 COUT
        2. 8.2.2.2 Softstart
        3. 8.2.2.3 Multiplier
        4. 8.2.2.4 Voltage Loop
        5. 8.2.2.5 Current Loop
        6. 8.2.2.6 Start Up
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Switch Selection
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Capacitor Ripple Reduction
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • N|16
  • DW|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

D, DW, N, and PW Packages
16 Pins
Top View
UCC2817 UCC2818 UCC3817 UCC3818 slus395_po.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
GND 1 – Ground. All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND with a 0.1-μF or larger ceramic capacitor.
PKLMT 2 I PFC peak current limit. The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense resistor to VREF to level shift this signal to a voltage level defined by the value of the sense resistor and the peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V.
CAOUT 3 O Current amplifier output. This is the output of a wide bandwidth operational amplifier that senses line current and commands the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed between CAOUT and MOUT.
CAI 4 I Current amplifier noninverting input. Place a resistor between this pin and the GND side of current sense resistor. This input and the inverting input (MOUT) remain functional down to and below GND.
MOUT 5 I/O Multiplier output and current amplifier inverting input. The output of the analog multiplier and the inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge modulation operation. The multiplier output current is limited to (2 × IIAC). The multiplier output current is given by the equation:
Equation 1. UCC2817 UCC2818 UCC3817 UCC3818 slus395_eq1.gif

where

  • K = 1/V is the multiplier gain constant
IAC 6 I Current proportional to input voltage. This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier is tailored for very low distortion from this current input (IIAC) to multiplier output. The recommended maximum IIAC is 500 μA.
VAOUT 7 O Voltage amplifier output. This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot.
VFF 8 I Feed-forward voltage. The RMS voltage signal generated at this pin by mirroring 1/2 of the IIAC into a single pole external filter. At low line, the VFF voltage should be 1.4 V.
VREF 9 O Voltage reference output. VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA to peripheral circuitry, and is internally short-circuit current-limited. VREF is disabled and remains at 0 V when VVCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-μF or larger ceramic capacitor for best stability. Refer to Figure 1 and Figure 2 for VREF line and load regulation characteristics.
OVP/EN 10 I Over-voltage/enable. A window comparator input that disables the output driver if the boost output voltage is a programmed level above the nominal ,or disables both the PFC output driver and resets SS if pulled below 1.9 V (typ).
VSENSE 11 I Voltage amplifier inverting input. This is normally connected to a compensation network and to the boost converter output through a divider network.
RT 12 I Oscillator charging current. A resistor from RT to GND is used to program oscillator charging current. A resistor between 10 kΩ and 100 kΩ is recommended. Nominal voltage on this pin is 3 V.
SS 13 I Soft-start. VSS is discharged for VVCC low conditions. When enabled, SS charges an external capacitor with a current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly. In the event of a VVCC dropout, the OVP/EN is forced below 1.9 V (typ), SS quickly discharges to disable the PWM. Note: In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. See the Application and Implementation for details.
CT 14 I

Oscillator timing capacitor. A capacitor from CT to GND sets the PWM oscillator frequency according to:

Equation 2. f ≈ 0.6/(RT × CT)

The lead from the oscillator timing capacitor to GND should be as short and direct as possible.
VCC 15 I Positive supply voltage. Connect to a stable source of at least 20 mA between 10 V and 17 V for normal operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless VVCC exceeds the upper undervoltage lockout voltage threshold and remains above the lower threshold.
DRVOUT 16 O Gate drive. The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. Use a series gate resistor to prevent interaction between the gate impedance and the output driver that might cause the DRVOUT to overshoot excessively. See Figure 6 to determine minimum required gate resister value. Some overshoot of the DRVOUT output is always expected when driving a capacitive load.