JAJS124Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select Rectifier Diodes
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, RR, DA)
          1. 8.2.2.10.1 Output Voltage Setpoint
          2. 8.2.2.10.2 Voltage Loop Compensation
          3. 8.2.2.10.3 Setting the Switching Frequency
          4. 8.2.2.10.4 Soft Start
          5. 8.2.2.10.5 Setting the Switching Delays
          6. 8.2.2.10.6 Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
      2. 11.1.2 関連リンク
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1 Layout Guidelines

In order to increase the reliability and robustness of the design, it is recommended that the following layout guidelines are followed.

  • EAN pin - This is the inverting input to the error amplifier. It is a high impedance pin and is susceptible to noise pickup. Keep tracks from this pin as short as possible.
  • EAP pin - This is the non-inverting input to the error amplifier. It is a high impedance pin and is susceptible to noise pickup. Keep tracks from this pin as short as possible.
  • EAOUT - pin Keep tracks from this pin as short as possible.
  • RAMP,CT, RT, DELAB, DELCD and ADS pins - The components connected to these pins are used to set important operating parameters. Keep these components close to the IC and provide short, low impedance return connections to the GND pin.
  • REF pin - Decouple this pin to GND with a good quality ceramic capacitor. A 1-µF, X7R, 25-V capacitor is recommended. Keep REF PCB tracks as far away as possible from sources of switching noise.
  • SYNC pin - This pin is essentially a digital I/O port. If it is unused, then it may be left open circuit. If Synchronisation is used, then route the incoming Synchronisation signal as far away from noise sensitive input pins as possible.
  • CS pin - This connection is arguably the most important single connection in the entire PSU system. Avoid running the CS signal traces near to sources of high dv/dt. Provide a simple RC filter as close as possible to the pin to help filter out leading edge noise spikes which will occur at the beginning of each switching cycle.
  • SS/DISB pin - Keep tracks from this pin as short as possible. If the Enable signal is coming from a remote source then avoid running it close to any source of high dv/dt (MOSFET Drain connections for example) and add a simple RC filter at the SS/DISB pin.
  • OUTA, OUTB, OUTC, and OUTD pins - These are the gate drive output pins and will have a high dv/dt rate associated with their rising and falling edges. Keep the tracks from these pins as far away from noise sensitive input pins as possible. Ensure that the return currents from these outputs do not cause voltage changes in the analog ground connections to noise sensitive input pins.
  • VDD pin - This pin must be decoupled to PGND using ceramic capacitors as detailed in the Power Supply Recommendations section. Keep this capacitor as close to the VDD and PGND pins as possible.
  • GND pin - This pin provides the analog ground reference to the controller. Use this pin to provide a return path for the components at the RAMP, REF, CT, RT, DELAB, DELCD, ADS, CS, and SS/DISB pins. Use a Ground Plane to minimise the impedance of the ground connection and to reduce noise pickup. It is important to have a low impedance connection from GND to PGND.
  • PGND pin - This pin provides the ground reference to the controller. This pin should be used to return the currents from the OUTX and SYNC pins. Use a Ground Plane to minimise the impedance of the ground connection and to reduce noise pickup.

An ideal ground plane provides an equipotential surface to which the controller ground pins can be connected. However, real ground planes have a non-zero impedance and having separate ground planes for analog and driver circuits is an easy way to prevent the analog ground from being disturbed by driver return currents. A single ground plane may be used if care is taken to ensure that the driver return currents are kept away from the part of the ground plane used for analog connections.