JAJSRJ4 October   2023 UCC44273

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Undervoltage Lockout
      2. 7.3.2 Operating Supply Current
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Low Propagation Delays
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Threshold Type
        2. 8.2.2.2 VDD Bias Supply Voltage
        3. 8.2.2.3 Peak Source and Sink Currents
        4. 8.2.2.4 Propagation Delay
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
      4. 8.4.4 Power Dissipation
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1 Design Requirements

When selecting the proper gate driver device for an end application, some design considerations must be evaluated first to make the most appropriate selection. Among these considerations are input-to-output configuration, the input threshold type, bias supply voltage levels, peak source and sink currents, propagation delay, power dissipation, and package type.

Table 8-1 Design Parameters
DESIGN PARAMETEREXAMPLE VALUE
Input-to-Output LogicNon-Inverting
Input Threshold TypeLogic Level
VDD Bias Supply Voltage10 V (minimum), 13 V (nominal), 15 V (peak)
Peak Source and Sink CurrentsMinimum 3 A Source, Minimum 3 A Sink
Propagation DelayMaximum 40 ns or Less