8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC5304 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks between the VDD and VSS pins. When the VDD bias voltage is lower than V_{VDD_ON} at device start-up or lower than V_{VDD_OFF} after start-up, the VDD UVLO feature holds the effected output low, regardless of the status of the IN pin.

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 20). In this condition, the upper PMOS is resistively held off by R_Hi-Z while the lower NMOS gate is tied to the driver output through R_CLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device, typically around 1.5V, when no bias power is available.

Figure 20. Simplified Representation of Active Pull Down Feature

The VDD UVLO protection has a hysteresis feature (V_{VDD_HYS}). This hysteresis prevents chatter when there is ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is bound to happen when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC5304 also has an internal under voltage lock out (UVLO) protection feature. The device isn't active unless the VCCI voltage exceeds V_{VCCI_ON} on start up. The input signal will not be delivered when the VCCI suply is less than V_{VCCI_OFF}. And, just like the UVLO for VDD, there is hystersis (V_{VCCI_HYS}) to ensure stable operation.