SLUSF94C December   2023  – June 2024 UCC57102-Q1 , UCC57108-Q1

PRODMIX  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Enable Function
      3. 6.3.3 Driver Stage
      4. 6.3.4 Desaturation (DESAT) Protection
      5. 6.3.5 Fault (FLT)
    4. 6.4 Device Functional Modes
  8. Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Undervoltage Lockout
      3. 7.2.3 Application Curves
  9. Power Supply Recommendations
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ(パッケージ|ピン)
  • D|8
サーマルパッド・メカニカル・データ
発注情報

Driver Stage

The device has a ±3-A peak drive strength and is suitable for driving IGBT/SiC. The driver features an important safety function wherein, when the input pins are in a floating condition, the output is held in the LOW state. The driver has rail-to-rail output by implementing an NMOS pull-up with intrinsic bootstrap gate drive. Under DC conditions, a PMOS is used to keep OUT tied to VDD as shown in the following figure. The low pullup impedance of the NMOS results in strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of the power semiconductor and reduces the turn on switching loss.

UCC57108-Q1 UCC57102-Q1 Gate Driver
                                        Output Stage Figure 6-4 Gate Driver Output Stage