SLUSFL3B June   2024  – October 2024 UCC57102 , UCC57108

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Enable Function
      3. 6.3.3 Driver Stage
      4. 6.3.4 Desaturation (DESAT) Protection
      5. 6.3.5 Fault (FLT)
      6. 6.3.6 VREF
      7. 6.3.7 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Undervoltage Lockout
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

5.6 Switching Characteristics

VDD = 15 V, VEE = 0 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VEE to GND, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted. (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tRA, tRB Output Rise Time CL=1.8nF, 10% to 90%, Vin = 0 to 3.3V 8 18 ns
tFA, tFB Output Fall Time CL=1.8nF, 90% to 10%, Vin = 0 to 3.3V 14 32 ns
tD2 Propagation Delay – Input falling to output falling CL=1.8nF, from 1V falling on Vin to 90% of output fall, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle 28 50 ns
tD1 Propagation Delay – Input rising to output rising CL=1.8nF, from 2V rising on Vin to 10% of output rise, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle 26 50 ns
tPD_EN EN Response Delay (W Version) CL=1.8nF, from 2V rising on EN to 10% of output rise, EN=0 - 3.3V, Fsw=500kHz, 50% duty cycle 26 40 ns
tPD_DIS DIS Response Delay (W Version) CL=1.8nF, from 1V falling on EN to 90% of output fall, EN=0 - 3.3V, Fsw=500kHz, 50% duty cycle 27 45 ns
tPWmin Minimum Input Pulse Width That Passes to Output CL=1.8nF, Vin=0 - 3.3V, Fsw=500kHz, Vo >2V 9 15 ns
tPWD Pulse Width Distortion Input Pulse Width = 100ns,  500kHz
tD2 – tD1,CL=1.8nF		 -10 10 ns
(1) Switching parameters are not tested in production.