JAJSTC9A December 2023 – March 2024 UCC57108-Q1
ADVMIX
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tRA, tRB | Output Rise Time | CL=1.8nF, 10% to 90%, Vin = 0 to 3.3V | 8 | 18 | ns | |
tFA, tFB | Output Fall Time | CL=1.8nF, 90% to 10%, Vin = 0 to 3.3V | 14 | 32 | ns | |
tD2 | Propagation Delay – Input falling to output falling | CL=1.8nF, from 1V falling on Vin to 90% of output fall, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle | 28 | 50 | ns | |
tD1 | Propagation Delay – Input rising to output rising | CL=1.8nF, from 2V rising on Vin to 10% of output rise, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle | 26 | 50 | ns | |
tPD_EN | EN Response Delay (W Version) | CL=1.8nF, from 2V rising on EN to 10% of output rise, EN=0 - 3.3V, Fsw=500kHz, 50% duty cycle | 26 | 40 | ns | |
tPD_DIS | DIS Response Delay (W Version) | CL=1.8nF, from 1V falling on EN to 90% of output fall, EN=0 - 3.3V, Fsw=500kHz, 50% duty cycle | 27 | 45 | ns | |
tPWmin | Minimum Input Pulse Width That Passes to Output | CL=1.8nF, Vin=0 - 3.3V, Fsw=500kHz, Vo >2V | 9 | 15 | ns | |
tPWD | Pulse Width Distortion | Input Pulse Width = 100ns, 500kHz tD2_1 – tD1_1 ,CL=1.8nF |
-10 | 10 | ns |