SLUSFL3B June   2024  – October 2024 UCC57102 , UCC57108

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Enable Function
      3. 6.3.3 Driver Stage
      4. 6.3.4 Desaturation (DESAT) Protection
      5. 6.3.5 Fault (FLT)
      6. 6.3.6 VREF
      7. 6.3.7 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Undervoltage Lockout
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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発注情報

4 Pin Configuration and Functions

UCC57108 UCC57102 UCC5710xB D Package SOIC-8 Top View Figure 4-1 UCC5710xB D Package SOIC-8 Top View
UCC57108 UCC57102 UCC5710xC D Package SOIC-8 Top View Figure 4-2 UCC5710xC D Package SOIC-8 Top View
UCC57108 UCC57102 UCC5710xW D Package SOIC-8 Top View Figure 4-3 UCC5710xW D Package SOIC-8 Top View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME UCC5710xB UCC5710xC UCC5710xW
IN 1 1 1 I Non-inverting PWM input
VREF 2 2 NA O 5V Reference generated within the driver
NC NA NA 2 Not Connected
FLTb 3 3 3 O Active low fault reporting
DESAT 4 4 4 I Input for detecting the desatuation fault
VDD 5 5 5 P Driver bias supply
OUT 6 NA 6 O Output of the driver
OUTH NA 6 NA O Driver high output
EN NA NA 6 I Enable or disable control pin.
OUTL NA 7 NA O Driver low output
GND 7 8 8 G Driver ground
VEE 8 NA NA P Driver negtive bias supply with respect to GND
(1) I/O = Digital input/output, IA = Analog input, AO= Analog output, P = Power connection