JAJSKM1C october 2019 – september 2021 UCC5870-Q1
PRODUCTION DATA
The active high voltage clamping feature protects power transistors from over-voltage damage during switching transitions, while reducing the power dissipated in the external TVS clamp diodes protecting the power FET. During turn-off, the VCECLP input is monitored. Once the VCE of the FET increases to turn on the external TVS diode, the RC network on the VCECLP input is charged up. Once the VCECLP input reaches the clamp threshold (VCECLPTH), OUTL drive strength changes to the ISTO setting in order to slow down the turn off and reduce the overshoot. The high voltage clamping remains active for a predefined time tVCECLP_HLD. The OV condition is reported in STATUS3[VCEOV_FAULT] (STATUS3). The implementation and timing diagrams for the active high voltage clamping are presented in Figure 7-22 and Figure 7-23, respectively. The VCECLP feature is enabled/disabled using the CFG4[VCECLP_EN] bit (CFG4).