JAJSKM1C
october 2019 – september 2021
UCC5870-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Electrical Characteristics
6.8
SPI Timing Requirements
6.9
Switching Characteristics
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power Supplies
7.3.1.1
VCC1
7.3.1.2
VCC2
7.3.1.3
VEE2
7.3.1.4
VREG1
7.3.1.5
VREG2
7.3.1.6
VREF
7.3.1.7
Other Internal Rails
7.3.2
Driver Stage
7.3.3
Integrated ADC for Front-End Analog (FEA) Signal Processing
7.3.3.1
AI* Setup
7.3.3.2
ADC Setup and Sampling Modes
7.3.3.2.1
Center Sampling Mode
7.3.3.2.2
Edge Sampling Mode
7.3.3.2.3
Hybrid Mode
7.3.3.3
DOUT Functionality
7.3.4
Fault and Warning Classification
7.3.5
Diagnostic Features
7.3.5.1
Undervoltage Lockout (UVLO) and Overvoltage Lockout (OVLO)
7.3.5.1.1
Built-In Self Test (BIST)
7.3.5.1.1.1
Analog Built-In Self Test (ABIST)
7.3.5.1.1.2
Function BIST
7.3.5.1.1.3
Clock Monitor
7.3.5.1.1.3.1
Clock Monitor Built-In Self Test
7.3.5.2
CLAMP, OUTH, and OUTL Clamping Circuits
7.3.5.3
Active Miller Clamp
7.3.5.4
DESAT based Short Circuit Protection (DESAT)
7.3.5.5
Shunt Resistor based Overcurrent Protection (OCP) and Short Circuit Protection (SCP)
7.3.5.6
Temperature Monitoring and Protection for the Power Transistors
7.3.5.7
Active High Voltage Clamping (VCECLP)
7.3.5.8
Two-Level Turn-Off
7.3.5.9
Soft Turn-Off (STO)
7.3.5.10
Thermal Shutdown (TSD) and Temperature Warning (TWN) of Driver IC
7.3.5.11
Active Short Circuit Support (ASC)
7.3.5.12
Shoot-Through Protection (STP)
7.3.5.13
Gate Voltage Monitoring and Status Feedback
7.3.5.14
VGTH Monitor
7.3.5.15
Cyclic Redundancy Check (CRC)
7.3.5.15.1
Calculating CRC
7.3.5.16
Configuration Data CRC
7.3.5.17
SPI Transfer Write/Read CRC
7.3.5.17.1
SDI CRC Check
7.3.5.17.2
SDO CRC Check
7.3.5.18
TRIM CRC Check
7.4
Device Functional Modes
7.4.1
State 1: RESET
7.4.2
State 2: Configuration 1
7.4.3
State 3: Configuration 2
7.4.4
State 4: Active
7.5
Programming
7.5.1
SPI Communication
7.5.1.1
System Configuration of SPI Communication
7.5.1.1.1
Independent Slave Configuration
7.5.1.1.2
Daisy Chain Configuration
7.5.1.1.3
Address-based Configuration
7.5.1.2
SPI Data Frame
7.5.1.2.1
Writing a Register
7.5.1.2.2
Reading a Register
7.6
Register Maps
7.6.1
UCC5870 Registers
8
Applications and Implementation
8.1
Application Information
8.1.1
Power Dissipation Considerations
8.1.2
Device Addressing
8.2
Typical Application Using Internal ADC Reference and Power FET Sense Current Monitoring
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
VCC1, VCC2, and VEE2 Bypass Capacitors
8.2.2.2
VREF, VREG1, and VREG2 Bypass Capacitors
8.2.2.3
Bootstrap Capacitor (VBST)
8.2.2.4
VCECLP Input
8.2.2.5
External CLAMP Output
8.2.2.6
AI* Inputs
8.2.2.7
OUTH/ OUTL Outputs
8.2.2.8
nFLT* Outputs
8.2.3
Application Curves
8.3
Typical Application Using DESAT Power FET Monitoring
8.3.1
Detailed Design Procedure
8.3.1.1
DESAT Input
8.3.2
Application Curves
9
Power Supply Recommendations
9.1
VCC1 Power Supply
9.2
VCC2 Power Supply
9.3
VEE2 Power Supply
9.4
VREF Supply (Optional)
10
Layout
10.1
Layout Guidelines
10.1.1
Component Placement
10.1.2
Grounding Considerations
10.1.3
High-Voltage Considerations
10.1.4
Thermal Considerations
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
サポート・リソース
11.4
Trademarks
11.5
静電気放電に関する注意事項
11.6
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DWJ|36
MPSS110A
サーマルパッド・メカニカル・データ
発注情報
jajskm1c_oa
jajskm1c_pm
8.3
Typical Application Using DESAT Power FET Monitoring
Figure 8-7
Typical Application Circuit using DESAT Overcurrent Protection